SCLS373N May   1996  – July 2024 SN74AHC595

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: VCC = 3.3 V ± 0.3 V
    7. 5.7  Timing Requirements: VCC = 5 V ± 0.5 V
    8. 5.8  Switching Characteristics: VCC = 3.3 V ± 0.3 V
    9. 5.9  Switching Characteristics: VCC = 5 V ± 0.5 V
    10. 5.10 Operating Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.4 Device Functional Modes

Table 7-1 Function Table
INPUTSFUNCTION
SERSRCLKSRCLRRCLKOE
XXXXHOutputs QA−QH are disabled.
XXXXLOutputs QA−QH are enabled.
XXLXXShift register is cleared.
L↑HXXFirst stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H↑HXXFirst stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
XXX↑XShift-register data is stored into the storage register.