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SN74LV1T08 Single Power Supply 2-Input Positive AND Gate CMOS Logic Level Shifter
SCLS739E
September 2013 – March 2024
SN74LV1T08
PRODUCTION DATA
CONTENTS
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SN74LV1T08 Single Power Supply 2-Input Positive AND Gate CMOS Logic Level Shifter
1
1
Features
2
Applications
3
Description
4
Related Products
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Operating Characteristics
6.8
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Balanced CMOS Push-Pull Outputs
8.3.2
LVxT Enhanced Input Voltage
8.3.2.1
Up Translation
8.3.2.2
Down Translation
8.3.3
Clamp Diode Structure
8.4
Device Functional Modes
9
Application and Implementation
9.1
Power Supply Recommendations
9.2
Layout
9.2.1
Layout Guidelines
9.2.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support (Analog)
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
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Data Sheet
SN74LV1T08 Single Power Supply 2-Input Positive AND Gate CMOS Logic Level Shifter
1
Features
Single-supply voltage translator at 5.0V, 3.3V, 2.5V, and 1.8V V
CC
Operating range of 1.8V to 5.5V
Up translation:
1.2V
(1)
to 1.8V at 1.8V V
CC
1.5V
(1)
to 2.5V at 2.5V V
CC
1.8V
(1)
to 3.3V at 3.3V V
CC
3.3V to 5.0V at 5.0V V
CC
Down translation:
3.3V to 1.8V at 1.8V V
CC
3.3V to 2.5V at 2.5V V
CC
5.0V to 3.3V at 3.3V V
CC
Logic output is referenced to V
CC
Output drive:
8mA Output Drive at 5V
7mA Output Drive at 3.3V
3mA Output Drive at 1.8V
Characterized up to 50MHz at 3.3V V
CC
5V tolerance on input pins
–40°C to 125°C operating temperature range
Pb-free packages available: SC-70 (DCK)
2 × 2.1 × 0.65mm (height 1.1mm)
Latch-up performance exceeds 250mA per
JESD 17
Supports standard logic pinouts
CMOS output B compatible with AUP1G and LVC1G families
(1)
1.
Refer to the V
IH
/V
IL
and output drive for lower V
CC
condition.
2
Applications
Telecom
Portable applications
Servers
PC and notebooks
