SCLS925B May   2023  – April 2024 SN74LV1T04-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics - 1.8V VCC
    7. 5.7  Switching Characteristics - 2.5V VCC
    8. 5.8  Switching Characteristics - 3.3V VCC
    9. 5.9  Switching Characteristics - 5.0V VCC
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 Clamp Diode Structure
      3. 7.3.3 LVxT Enhanced Input Voltage
        1. 7.3.3.1 Down Translation
        2. 7.3.3.2 Up Translation
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω.

For clock inputs, fmax is measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

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(1) CL includes probe and test-fixture capacitance.
Figure 6-1 Load Circuit for Push-Pull Outputs
GUID-C776A044-2A5E-4922-80CB-F23FB71B60F6-low.gif
(1) The greater between tr and tf is the same as tt.
Figure 6-3 Voltage Waveforms, Input and Output Transition Times
GUID-196E44F9-39AE-47F9-89AA-22E024996D3A-low.gif
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-2 Voltage Waveforms Propagation Delays