SCLS951A August   2023  – November 2023 SN74LV8T165-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LVxT Enhanced Input Voltage
        1. 7.3.1.1 Down Translation
        2. 7.3.1.2 Up Translation
      2. 7.3.2 Balanced CMOS Push-Pull Outputs
      3. 7.3.3 Latching Logic with Known Power-Up State
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC TA = 25°C -40°C to 125°C UNIT
MIN MAX MIN MAX
fCLOCK Clock frequency 1.8 V 37.7 27.8 MHz
tW Pulse duration SH/LD low 6.1 6.9 ns
CLK high or low 6.1 7
tSU Setup time SH/LD high before CLK↑ 6.3 8
SER before CLK↑ 7.9 10.1
CLK INH low before CLK↑ 1 1
CLK INH high before CLK↑ 1 1
Data before SH/LD↓ 8.3 10
tH Hold time SER data after CLK↑ 0 0
PAR data after SH/LD↓ 0 0
fCLOCK Clock frequency 2.5 V 53.9 39.7 MHz
tW Pulse duration SH/LD low 4.3 5.4 ns
CLK high or low 4.3 4.5
tSU Setup time SH/LD high before CLK↑ 3.3 4.5
SER before CLK↑ 4.5 5.9
CLK INH low before CLK↑ 1 1
CLK INH high before CLK↑ 1 1
Data before SH/LD↓ 5.7 6.9
tH Hold time SER data after CLK↑ 0 0
PAR data after SH/LD↓ 0 0
fCLOCK Clock frequency 3.3 V 77 56.7 MHz
tW Pulse duration SH/LD low 4.3 4.3 ns
CLK high or low 4.3 4.3
tSU Setup time SH/LD high before CLK↑ 2.2 2.9
SER before CLK↑ 3.2 4
CLK INH low before CLK↑ 1 1
CLK INH high before CLK↑ 1 1
Data before SH/LD↓ 4.5 5.3
tH Hold time SER data after CLK↑ 0 0
PAR data after SH/LD↓ 0 0
fCLOCK Clock frequency 5 V 110 81 MHz
tW Pulse duration SH/LD low 4.3 4.3 ns
CLK high or low 4.3 4.3
tSU Setup time SH/LD high before CLK↑ 1.4 1.9
SER before CLK↑ 1.3 1.8
CLK INH low before CLK↑ 1 1
CLK INH high before CLK↑ 1 1
Data before SH/LD↓ 2.6 3.1
tH Hold time SER data after CLK↑ 0 0
PAR data after SH/LD↓ 0 0