SCLS996A January   2024  – April 2024 SN74AC595-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC TA = 25°C -40°C to 85°C -40°C to 125°C UNIT
MIN MAX MIN MAX MIN MAX
fCLOCK Clock frequency 1.5 V 20 MHz
1.8 V 25 MHz
2.5 V 50 MHz
3.3 V 55 MHz
5 V 90 MHz
tW Pulse duration RCLK or SRCLK high or low 1.5 V 13 ns
1.8 V 8 ns
2.5 V 6 ns
3.3 V 4 ns
5 V 2 ns
SRCLR low 1.5 V 7 ns
1.8 V 6 ns
2.5 V 4 ns
3.3 V 3 ns
5 V 2 ns
tSU Setup time SER before SRCLK↑ 1.5 V 8 ns
1.8 V 5 ns
2.5 V 3 ns
3.3 V 2 ns
5 V 1 ns
SRCLK↑ before RCLK↑ 1.5 V 25 ns
1.8 V 15 ns
2.5 V 9 ns
3.3 V 6 ns
5 V 4 ns
SRCLR low before RCLK↑ 1.5 V 17 ns
1.8 V 11 ns
2.5 V 7 ns
3.3 V 5 ns
5 V 3 ns
SRCLR high (inactive) before SRCLK↑ 1.5 V 2 ns
1.8 V 1 ns
2.5 V 1 ns
3.3 V 1 ns
5 V 1 ns
tH Hold time SER after SRCLK↑ 1.5 V 7 ns
1.8 V 4 ns
2.5 V 3 ns
3.3 V 2 ns
5 V 2 ns