SCLSA20 June   2024 SN74LVC2G101-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Noise Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 CMOS Schmitt-Trigger Inputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Reference
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 Switching Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter Measurement Information
PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE VCC -40°C to 125°C UNIT
MIN TYP MAX
tpd CLK Q CL = 15pF 1.2V ± 0.1V 17.7 33 ns
tpd CLK Q CL = 15pF
1.5V ± 0.12V

 9.9 18 ns
tpd CLK Q CL = 30pF 1.8V ± 0.15V 7.7 13 ns
tpd CLK Q CL = 30pF 2.5V ± 0.2V 5.1 8 ns
tpd CLK Q CL = 50pF 2.7V 5 8 ns
tpd CLK Q CL = 50pF 3.3V ± 0.3V 4.7 7 ns
tpd CLR Q CL = 15pF
1.2V ± 0.1V

 29.8 51 ns
tpd CLR Q CL = 15pF
1.5V ± 0.12V

 11.8 19 ns
tpd CLR Q CL = 30pF 1.8V ± 0.15V 8.5 14 ns
tpd CLR Q CL = 30pF 2.5V ± 0.2V 5.7 10 ns
tpd CLR Q CL = 50pF 2.7V 5.5 9 ns
tpd CLR Q CL = 50pF 3.3V ± 0.3V 5.2 9 ns
tsk(o) 3.3V ± 0.3V 1 ns