SCPA063 March   2023 PCA9306

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2General Checks for Dealing With NACKs
    1. 2.1 NACKs
    2. 2.2 Check the Schematic
    3. 2.3 Double Check SDA and SCL Between the Controller and Target
    4. 2.4 RESET Properly Biased
    5. 2.5 Device is Soldered Properly
  5. 3Scopeshots
    1. 3.1 Why use Oscilloscopes for Debugging?
    2. 3.2 Setting up the Oscilloscope
    3. 3.3 Verify the I2C Address When a NACK is Received
    4. 3.4 Validate Start and Stop Conditions
    5. 3.5 Check the Byte Format
    6. 3.6 Are Rise Times Within I2C Standard?
    7. 3.7 Are the Sent Command Bytes Valid?
  6. 4I2C Switches
    1. 4.1 Stop Conditions for TI I2C Switches
  7. 5I2C Buffers
    1. 5.1 VoL versus ViLc of the Buffer
    2. 5.2 VoL of the Buffer Exceeds the ViL of the I2C Target
    3. 5.3 Static Offset of Buffers Cannot Connect to Other Static Offsets
  8. 6Checklists
  9. 7Conclusion

2.3 Double Check SDA and SCL Between the Controller and Target

If NACKs are being received from an I2C device the design is communicating with, check to make sure that the SDA and SCL lines are properly connected between the I2C controller and target. Sometimes users accidentally swap the SDA and SCL connections between a controller and target device. If this happens, the target device always sends NACKs back to the controller, even if the correct bits are being transmitted. To prevent this from happening, always verify that the SDA and SCL connections between the controller and the target are correct. Figure 2-4 shows an example where the SDA and SCL nets on the schematic are swapped with the schematic pinout SDA and SCL resulting in the I2C target device always NACKing the address.

GUID-20221012-SS0I-JLP1-ZK0P-07ZWVLPCBZK9-low.pngFigure 2-4 Example of SDA and SCL Nets Swapped in Schematic