SCPA063 March   2023 PCA9306

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2General Checks for Dealing With NACKs
    1. 2.1 NACKs
    2. 2.2 Check the Schematic
    3. 2.3 Double Check SDA and SCL Between the Controller and Target
    4. 2.4 RESET Properly Biased
    5. 2.5 Device is Soldered Properly
  5. 3Scopeshots
    1. 3.1 Why use Oscilloscopes for Debugging?
    2. 3.2 Setting up the Oscilloscope
    3. 3.3 Verify the I2C Address When a NACK is Received
    4. 3.4 Validate Start and Stop Conditions
    5. 3.5 Check the Byte Format
    6. 3.6 Are Rise Times Within I2C Standard?
    7. 3.7 Are the Sent Command Bytes Valid?
  6. 4I2C Switches
    1. 4.1 Stop Conditions for TI I2C Switches
  7. 5I2C Buffers
    1. 5.1 VoL versus ViLc of the Buffer
    2. 5.2 VoL of the Buffer Exceeds the ViL of the I2C Target
    3. 5.3 Static Offset of Buffers Cannot Connect to Other Static Offsets
  8. 6Checklists
  9. 7Conclusion

2.1 NACKs

In I2C communication, every transaction consists of 8 bits (1 byte) of information from the controller followed by one bit from the target device. The bit sent by the target device can either be a 0 (usually denoted as an ACK bit), or a 1 (usually denoted as a NACK bit). When an ACK bit is sent by the target, this indicates that the data transmission was correctly received without any errors. When a NACK bit is sent by the target, this indicates that the receiver did not correctly receive the data or address transmission. There are several general conditions that can lead to the generation of a NACK in an I2C system. These conditions are detailed in ACK and NACK section of the Understanding the I2C Bus application note.

Figure 2-1 is an example which showcases a NACK occurring when the I2C controller tries to write to the target device at address 0x55h and the I2C target NACKs (does not drive SDA low on the 9th clock pulse).

GUID-20221012-SS0I-1C7Z-VPHC-VVN0RJKPPS6R-low.svg Figure 2-1 Example of NACK