SCPA069 July   2024 TCA4307

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1What is a Stuck Bus?
  5. 2How can a Stuck Bus Occur?
  6. 3Crosstalk
  7. 4EMI
  8. 5Hot Insertion
  9. 6Resolving a Stuck Bus
  10. 7Conclusion
  11. 8References

How can a Stuck Bus Occur?

A stuck bus can occur in several different ways, the main offender for most cases is a false clock edge being generated. The reason why a false clock edge is dangerous on the I2C bus is because a false clock edge desynchronizes the I2C target’s clock relative to the I2C controller, who is responsible for generating the clock edges. Differences between the I2C target device ns deglitch filter and the I2C controller’s deglitch filter can contribute to one device seeing the false edge while the other does not. An example is if the I2C target has a 70ns deglitch filter while the controller has a 50ns deglitch filter and a false edge occurs with a 60ns window which makes the controller see the edge but the target ignores the false edge. Another potential case is if there is an I2C redriver (also known as a buffer) between the target and the controller. If a false edge occurs on one side, it cannot propagate through the redriver so either the controller or the target can see the edge while the other does not.

An example is shown in Figure 2-1. The first transaction in this example shows what is supposed to happen. The controller is sending data to the target with the data package of 0x0Ah and at the 9th clock pulse the target ACKs to tell the controller that the target receives the data then a stop condition is generated by the controller. The second transaction is the same as the first, however a false edge is generated during the 5th clock pulse of which the controller sees but not the I2C target. This means the controller is one clock ahead in the I2C transaction while the I2C target is one clock behind. The data the target sees is then shifted to the left by one so it receives bad data (0x05h) instead of seeing 0x0Ah. When the 8th falling SCL edge comes (from the target’s perspective), the I2C target drives the SDA line low but never sees the 9th falling SCL edge. This results in the SDA line getting stuck low indefinitely. The controller cannot issue a stop condition and depending on the controller's hardware and software, can keep SCL low or release SCL.

 Example of False Edge on
                Controller During Write Transaction Figure 2-1 Example of False Edge on Controller During Write Transaction

Root causes for a stuck bus can come from crosstalk, electromagnetic interference, hot-insertion events, or bad power on reset situations.