SCPS133K December   2005  – December 2024 PCA9557

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Timing Requirements
    7. 5.7 Reset Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1 RESET
        1. 7.2.1.1 RESET Errata
          1. 7.2.1.1.1 System Impact
          2. 7.2.1.1.2 System Workaround
      2. 7.2.2 Power-On Reset
    3. 7.3 Programming
      1. 7.3.1 I2C Interface
    4. 7.4 Register Maps
      1. 7.4.1 Device Address
      2. 7.4.2 Control Register And Command Byte
      3. 7.4.3 Register Descriptions
        1. 7.4.3.1 Bus Transactions
          1. 7.4.3.1.1 Writes
          2. 7.4.3.1.2 Reads
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Minimizing ICC when I/O is Used to Control LED
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Errata
        1. 8.3.1.1 System Impact
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1)
MIN MAX UNIT
STANDARD MODE
fscl I2C clock frequency 100 kHz
tsch I2C clock high time 4 μs
tscl I2C clock low time 4.7 μs
tsp I2C spike time 50 ns
tsds I2C serial data setup time 250 ns
tsdh I2C serial data hold time 0 ns
ticr I2C input rise time 1000 ns
ticf I2C input fall time 300 ns
tocf I2C output fall time, 10-pF to 400-pF bus 300 ns
tbuf I2C bus free time between stop and start 4.7 μs
tsts I2C start or repeated start condition setup time 4.7 μs
tsth I2C start or repeated start condition hold time 4 μs
tsps I2C stop condition setup time 4 μs
tvd(data) Valid data time, SCL low to SDA output valid 1 μs
tvd(ack) Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low 1 μs
Cb I2C bus capacitive load 400 pF
FAST MODE
fscl I2C clock frequency 400 kHz
tsch I2C clock high time 0.6 μs
tscl I2C clock low time 1.3 μs
tsp I2C spike time 50 ns
tsds I2C serial data setup time 100 ns
tsdh I2C serial data hold time 0 ns
ticr I2C input rise time 20 + 0.1Cb (1) 300 ns
ticf I2C input fall time 20 + 0.1Cb (1) 300 ns
tocf I2C output fall time, 10-pF to 400-pF bus 20 + 0.1Cb (1) 300 ns
tbuf I2C bus free time between Stop and Start 1.3 μs
tsts I2C start or repeated start condition setup time 0.6 μs
tsth I2C start or repeated start condition hold time 0.6 μs
tsps I2C stop condition setup time 0.6 μs
tvd(data) Valid data time, SCL low to SDA output valid 0.9 μs
tvd(ack) Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low 0.9 μs
Cb I2C bus capacitive load 400 pF
(1) Cb = total capacitance of one bus line in pF