The V_REF1 pin can be supplied by a low-dropout regulator (LDO), but in some cases the LDO can lose its regulation because of the bias current from V_REF2 to V_REF1. If the LDO cannot sink the bias current, then the current has no other paths to ground and instead charges up the capacitance on the V_REF1 node (both external and parasitic). This results in an increase in voltage on the V_REF1 node. If no other paths for current to flow are established (such as back biasing of body diodes or clamping diodes through other devices on the V_REF1 node), then the V_REF1 voltage ends up stabilizing when V_gs of the pass FET is equal to V_th. This means V_REF1 node voltage is V_CC2 - V_th. Note that any target or controllers running off of the LDO now see the V_CC2 - V_th voltage which may cause damage to those target or controllers if they are not rated to handle the increased voltage.

Figure 9-8 Example of no leakage current path when using LDO

To ensure LDO does not lose regulation due to the bias current of PCA9306-Q1, a weak pull down resistor can be placed on V_REF1 to ground to provide a path for the bias current to travel. The recommended pull down resistor is calculated by Equation 4 where 0.75 gives about 25% margin for error incase bias current increases during operation.

Figure 9-9 Example with Leakage current path when using an LDO

where

• V_th is approximately 0.6 V