SCPS178C July   2007  – April 2022 PCA9306-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: Translating Down, VIH = 3.3 V
    7. 7.7  Switching Characteristics: Translating Down, VIH = 2.5 V
    8. 7.8  Switching Characteristics: Translating Up, VIH = 2.3 V
    9. 7.9  Switching Characteristics: Translating Up, VIH = 1.5 V
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Definition of threshold voltage
      2. 9.1.2 Correct Device Set Up
      3. 9.1.3 Disconnecting a Target from the Main I2C Bus Using the EN Pin
      4. 9.1.4 Supporting Remote Board Insertion to Backplane with PCA9306-Q1
      5. 9.1.5 Switch Configuration
      6. 9.1.6 Controller on Side 1 or Side 2 of Device
      7. 9.1.7 LDO and PCA9306-Q1 Concerns
      8. 9.1.8 Current Limiting Resistance on VREF2
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Enable (EN) Pin
      2. 9.3.2 Voltage Translation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 General Applications of I2C
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Bidirectional Translation
        2. 10.2.2.2 Sizing Pullup Resistor
        3. 10.2.2.3 PCA9306-Q1 Bandwidth
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

9.1.2 Correct Device Set Up

In a normal set up shown in Figure 9-1, the enable pin and VREF2 are shorted together and tied to a 200-kΩ resistor, and a reference voltage equal to VREF1 plus the FET threshold voltage is established. This reference voltage is used to help pass lows from one side to another more effectively while still separating the different pull up voltages on both sides.

GUID-F75DD36F-8785-4415-A2AC-C6A5488E53F4-low.gifFigure 9-1 Normal Setup

Care should be taken to ensure VREF2 has an external resistor tied between it and VCC2. If VREF2 is tied directly to the VCC2 rail without a resistor, then there is no external resistance from the VCC2 to VCC1 to limit the current such as in Figure 9-2. This effectively looks like a low impedance path for current to travel through and potentially break the pass FET if the current flowing through the pass FET is larger than the absolute maximum continuous channel current specified in section 6.1. The continuous channel current is larger with a higher voltage difference between VCC1 and VCC2.

Figure 9-2 shows an improper set up. If VCC2 is larger than VCC1 but less than Vth, the impedance between VCC1 and VCC2 is high resulting in a low drain to source current, which does not cause damage to the device. Concern arises when VCC2 becomes larger than VCC1 by Vth. During this event, the NFET turns on and begin to conduct current. This current is dependent on the gate to source voltage and drain to source voltage.

GUID-EFBEDBA3-6B2F-4F34-9C2C-452462BFA7BA-low.gifFigure 9-2 Abnormal Setup