SCPS178C July   2007  – April 2022 PCA9306-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: Translating Down, VIH = 3.3 V
    7. 7.7  Switching Characteristics: Translating Down, VIH = 2.5 V
    8. 7.8  Switching Characteristics: Translating Up, VIH = 2.3 V
    9. 7.9  Switching Characteristics: Translating Up, VIH = 1.5 V
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Definition of threshold voltage
      2. 9.1.2 Correct Device Set Up
      3. 9.1.3 Disconnecting a Target from the Main I2C Bus Using the EN Pin
      4. 9.1.4 Supporting Remote Board Insertion to Backplane with PCA9306-Q1
      5. 9.1.5 Switch Configuration
      6. 9.1.6 Controller on Side 1 or Side 2 of Device
      7. 9.1.7 LDO and PCA9306-Q1 Concerns
      8. 9.1.8 Current Limiting Resistance on VREF2
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Enable (EN) Pin
      2. 9.3.2 Voltage Translation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 General Applications of I2C
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Bidirectional Translation
        2. 10.2.2.2 Sizing Pullup Resistor
        3. 10.2.2.3 PCA9306-Q1 Bandwidth
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

10.2.2.3 PCA9306-Q1 Bandwidth

The maximum frequency of the PCA9306-Q1 device depends on the application. The device can operate at speeds of > 100 MHz given the correct conditions. The maximum frequency is dependent upon the loading of the application. The PCA9306-Q1 device behaves like a standard switch where the bandwidth of the device is dictated by the ON-resistance and ON-capacitance of the device.

Figure 10-5 shows a bandwidth measurement of the PCA9306-Q1 device using a two-port network analyzer.

The 3-dB point of the PCA9306-Q1 device is approximately 600 MHz. However, this is an analog type of measurement. For digital applications, the signal must not degrade up to the fifth harmonic of the digital signal. As a rule of thumb, the frequency bandwidth must be at least five times the maximum digital clock rate. This component of the signal is very important in determining the overall shape of the digital signal. In the case of the PCA9306-Q1 device, digital clock frequency of > 100 MHz can be achieved.

The PCA9306-Q1 device does not provide any drive capability like the PCA9515 or PCA9517 series of devices. Therefore, higher-frequency applications require higher drive strength from the host side. No pullup resistor is needed on the host side (3.3 V) if the PCA9306-Q1 device is being driven by standard CMOS push-pull output driver. Ideally, it is best to minimize the trace length from the PCA9306-Q1 device on the sink side (1.8 V) to minimize signal degradation.

You can then use a simple formula to compute the maximum practical frequency component or the knee frequency (fknee). All fast edges have an infinite spectrum of frequency components. However, there is an inflection (or knee) in the frequency spectrum of fast edges where frequency components higher than fknee are insignificant in determining the shape of the signal.

To calculate fknee:

Equation 8. fknee = 0.5 / RT (10–90%)
Equation 9. fknee = 0.4 / RT (20–80%)

For signals with rise-time characteristics based on 10- to 90-percent thresholds, fknee is equal to 0.5 divided by the rise time of the signal. For signals with rise-time characteristics based on 20- to 80-percent thresholds, which is very common in many current device specifications, fknee is equal to 0.4 divided by the rise time of the signal.

Some guidelines to follow that help maximize the performance of the device:

  • Keep trace length to a minimum by placing the PCA9306-Q1 device close to the I2C output of the processor.
  • The trace length must be less than half the time of flight to reduce ringing and line reflections or non-monotonic behavior in the switching region.
  • To reduce overshoots, a pullup resistor can be added on the 1.8-V side; be aware that a slower fall time is to be expected.