SCPS272C October   2019  – January 2021 TCA9511A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hot bus insertion
      2. 8.3.2 Pre-charge voltage
      3. 8.3.3 Rise time accelerators
      4. 8.3.4 Bus ready output indicator
      5. 8.3.5 Powered-off high impedance for I2C and I/O pins
      6. 8.3.6 Supports clock stretching and arbitration
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-up and precharge
      2. 8.4.2 Bus idle
      3. 8.4.3 Bus active
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Series connections
        2. 9.2.1.2 Multiple connections to a common node
        3. 9.2.1.3 Propagation delays
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application on a Backplane
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Best Practices
    2. 10.2 Power-on Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

11.1 Layout Guidelines

For printed circuit board (PCB) layout of the TCA9511A, common PCB layout practices should be followed but additional concerns related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C signal speeds. In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller capacitor to filter out high frequency ripple. These capacitors should be placed as close to the TCA9511A as possible. These best practices are shown in Section 11.2.

The layout example provided in Section 11.2 shows a 4 layer board, which is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly next to the surface mount component pad which needs to attach to VCC or GND and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace needs to be routed to the opposite side of the board, shown in the Section 11.2 for the VCC side of the resistor connected to the EN pin; however, this routing and via is not necessary if VCC and GND are both full planes as opposed to the partial planes depicted.