SCPS301 September   2024 TPLD801-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
  7. 6Parameter Measurement Information
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT macro-cell
        2. 7.3.3.2 3-Bit LUT macro-cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop/Latch macro-cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch with Set/Reset macro-cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay macro-cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter/Delay macro-cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell
      6. 7.3.6 Selectable Frequency Oscillator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 One-Time Programmable Memory (OTP)
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Option Addendum
    2. 9.2 Tape and Reel Information
    3. 9.3 Mechanical Data

7.3.4.1 Delay Mode

When configured as a Delay generator (DLY), this macro-cell delays the input based on counter DATA and CLK input frequency and postpones rising and/or falling edges. The edge on which to delay is selected by the Edge select parameter and can be configured as:

  • Rising: only delay on rising edges of IN.

  • Falling: only delay on falling edges of IN.

  • Both: delay on both rising and falling edges of IN.

For delay applications, it is recommended to use larger counter data values for less error. If an input pulse width is shorter than the specified delay time, the pulse will be filtered out. This feature can be useful for deglitching.

If the on-chip oscillator is used, a delay error or offset is introduced depending on whether the OSC is set to "forced power on" or "auto power on". An additional 2 clock cycles are included in the delay calculation for clock synchronization, but there is an option to bypass the clock sync.

The delay time is calculated by DELAY = (DATA + (td_err or td_os) + 2)/fCLK.

When the OSC is set to "auto power on" and DLY macro-cells are triggered subsequently before the previous output is present, the OSC will continue to clock and the DLY will begin on the next rising edge. Thus, the subsequent delays can be calculated as if the OSC were set to "forced power on".

Figure 7-11 shows an example of the Delay macro-cell operation set to both edge delay and data = 1.

TPLD801-Q1 Delay output timing example (Both edge delay and DATA = 1)Figure 7-11 Delay output timing example (Both edge delay and DATA = 1)

Figure 7-12 shows an example timing of two different Delay macro-cells triggered consecutively with the OSC set to "auto power on".

TPLD801-Q1 Delay output timing example (2 Delay macro-cells, Both edge delay, DATA = 1, OSC power = auto)Figure 7-12 Delay output timing example (2 Delay macro-cells, Both edge delay, DATA = 1, OSC power = auto)