The TPLD801-Q1 has one internal oscillator, selectable to operate at 25kHz or at 2MHz. The user can select one of these operating frequencies for the OSC macro-cell, or the internal oscillator could be bypassed and the operating frequency can come from an external clock.

Figure 7-18 Oscillator Block Diagram

Following the operating clock input, there are two divider stages that allow users the flexibility of various clock frequencies for use throughout the device.

The first stage divider allows the selection of up to four options from the operating oscillator frequency as listed in Table 7-13. The output of the first divider stage is routed directly to the counter/delay generator macro-cell CLK inputs, where a separate second divider stage is available.

The output of the first divider stage is also routed into a second divider stage within the oscillator macro-cell. The oscillator macro-cell has two separate second stage dividers, allowing for the output of two separate clocks (OUT0 and OUT1) into the connection mux. See Table 7-14

Oscillator power modes: When using the device's internal oscillator, there are two configuration settings available:

• Force power on: the internal oscillator will continuously run as long as the device is powered on.
• Auto power on: the internal oscillator will dynamically power on when any macro-cell requests the oscillator directly from the pre-divider block output and not through the connection mux, and then power off once the task is complete.
• External power on/off: the internal oscillator will be powered down when PDWN is asserted High. PDWN signal takes priority over the oscillator power modes. This is only applicable when the internal oscillator is selected and is bypassed when an external clock is used.