SCPS301 September   2024 TPLD801-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
  7. 6Parameter Measurement Information
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT macro-cell
        2. 7.3.3.2 3-Bit LUT macro-cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop/Latch macro-cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch with Set/Reset macro-cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay macro-cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter/Delay macro-cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell
      6. 7.3.6 Selectable Frequency Oscillator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 One-Time Programmable Memory (OTP)
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Option Addendum
    2. 9.2 Tape and Reel Information
    3. 9.3 Mechanical Data

2-Bit LUT or D Flip-Flop/Latch macro-cell

This configurable use logic block can serve as either a 2-bit LUT, or as a D flip-flop or latch.

TPLD801-Q1 2-bit LUT or DFF/Latch Block DiagramFigure 7-4 2-bit LUT or DFF/Latch Block Diagram

When used to implement LUT functions, the 2-bit LUT takes in two input signals from the connection mux and produces a single output, which goes back into the connection mux. These LUTs can be configured to any 2-input user defined function, including the following standard digital logic functions: AND, NAND, OR, NOR, XOR, XNOR, INV.

Table 7-11 shows the truth table for a 2-bit LUT.

Table 7-4 2-bit LUT Truth Table
IN1IN0OUT
00

User defined

01
10
11
Each 2-bit LUT has 4 bits in the OTP to define their output function.

When used to implement a sequential logic element, the two input signals from the connection mux go to the data (D) and clock (CLK) inputs of the flip-flop or latch, with the output going back to the connection mux. This macro-cell has initial state parameters, as well as clock and output polarity parameters.

The operation of the D flip-flop/latch will follow the functional descriptions below:

  • The clock polarity is configurable and can be set to non-inverted (CLKPOL = 0, CLK) or inverted (CLKPOL = 1, nCLK).

    • DFF with CLK: CLK is rising edge triggered, then Q = D; otherwise Q will not change.

    • DFF with nCLK: CLK is falling edge triggered, then Q = D; otherwise Q will not change.

    • Latch with CLK: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is High).

    • Latch with nCLK: when CLK is High, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is Low).

  • The output polarity is configurable and can be set to non-inverted (Q) or inverted (nQ).

Table 7-8 and Table 7-9 show the truth tables for the D flip-flop and D latch, respectively.

Table 7-5 D Flip-Flop Truth Table

CLKPOL

CLK

D

Q

nQ

0

0

Q0

nQ0

0

0

1

1

Q0

nQ0

1

1

0

1

0

0

1

0

Q0

nQ0

1

1

0

1

Q0

nQ0

Table 7-6 D Latch Truth Table

CLKPOL

CLK

D

Q

nQ

0

0

0

0

1

1

0

Q0

nQ0

0

1

1

0

1

1

Q0

nQ0

1

0

0

Q0

nQ0

1

0

0

1

0

1

Q0

nQ0

1

1

1

0