SCPS301 September   2024 TPLD801-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
  7. 6Parameter Measurement Information
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT macro-cell
        2. 7.3.3.2 3-Bit LUT macro-cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop/Latch macro-cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch with Set/Reset macro-cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay macro-cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter/Delay macro-cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell
      6. 7.3.6 Selectable Frequency Oscillator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 One-Time Programmable Memory (OTP)
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Option Addendum
    2. 9.2 Tape and Reel Information
    3. 9.3 Mechanical Data

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Supply and Power-on Reset
VPORR Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 1.65V to 5.5V 1.04 1.30 1.50 V
VPORF Power-on reset voltage, VCC falling VI = VCC or GND, IO = 0 1.65V to 5.5V 0.98 1.17 1.33 V
tSU Startup time from VCC rising past VPORR 1.65V to 5.5V 270 µs
VPP Programming voltage 1.65V to 5.5V 7.5 8 8.5 V
Digital IO
VT+ Positive-going input threshold voltage Logic Input with Schmitt Trigger 1.8V ± 0.15V 0.92 1.29 V
3.3V ± 0.3V 1.55 2.17
5V ± 0.5V 2.21 3.19
VT- Negative-going input threshold voltage Logic Input with Schmitt Trigger 1.8V ± 0.15V 0.56 0.96 V
3.3V ± 0.3V 1.10 1.79
5V ± 0.5V 1.63 2.70
VHYS Schmitt trigger hysteresis (VT+ − VT−) Logic Input with Schmitt Trigger 1.8V ± 0.15V 0.23 0.49 V
3.3V ± 0.3V 0.33 0.54
5V ± 0.5V 0.42 0.66
VOH High-level output voltage Push-pull 1X or Open-drain PMOS 1X IOH = -100µA 1.8V ± 0.15V 1.626 V
Push-pull 2X or Open-drain PMOS 2X 1.636
VOH High-level output voltage Push-pull 1X or Open-drain PMOS 1X IOH = -3mA 3.3V ± 0.3V 2.710 V
Push-pull 2X or Open-drain PMOS 2X 2.820
VOH High-level output voltage Push-pull 1X or Open-drain PMOS 1X IOH = -5mA 5V ± 0.5V 4.120 V
Push-pull 2X or Open-drain PMOS 2X 4.240
VOL Low-level output voltage Push-pull 1X IOL = 100µA 1.8V ± 0.15V 0.009 V
Push-pull 2X 0.005
Open-drain NMOS 1X 0.009
Open-drain NMOS 2X 0.005
VOL Low-level output voltage Push-pull 1X IOL = 3mA 3.3V ± 0.3V 0.118 V
Push-pull 2X 0.076
Open-drain NMOS 1X 0.118
Open-drain NMOS 2X 0.076
VOL Low-level output voltage Push-pull 1X IOL = 5mA 5V ± 0.5V 0.139 V
Push-pull 2X 0.096
Open-drain NMOS 1X 0.139
Open-drain NMOS 2X 0.096
II Input leakage current All pins VI = VCC 1.65V to 5.5V ±1 µA
VI = GND 1.65V to 5.5V ±1
Rpu(int) Internal pull-up resistance 1 MΩ
100 kΩ
10 kΩ
Rpd(int) Internal pull-down resistance 1 MΩ
100 kΩ
10 kΩ
Rpd(int)_GPI Internal pull-down resistance - GPI/IN0 1 MΩ
100 kΩ
15 kΩ