SCPS304 September   2024 TPLD1201-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT Macro-Cell
        2. 7.3.3.2 3-Bit LUT Macro-Cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell
      6. 7.3.6 Selectable Frequency Oscillator
      7. 7.3.7 Analog Comparators (ACMP)
      8. 7.3.8 Voltage Reference (VREF)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Option Addendum
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

7.4.1 Power-On Reset

The TPLD1201-Q1 has a power-on reset (POR) macro-cell that provides correct device initialization and operation of all macro-cells in the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VCC power is first ramping to the device, and also while the VCC is falling during power-down. To accomplish this goal, the POR drives a defined sequence of internal events that trigger changes to the states of different macro-cells inside the device, and finally to the state of the I/O pins.

The power-on Reset (POR) macro-cell will produce a logic High signal as an output when the device power supply (VCC) rises to approximately VPORR and device completely starts up. All outputs are in high impedance state and chip starts loading data from OTP. The reset signal is released for internal macro-cells and all the registers are initialized to their default states. Figure 7-21 shows POR system generates a sequence of signals that enable certain macro-cells.

TPLD1201-Q1 POR SequenceFigure 7-21 POR Sequence

As shown in Figure 7-21, after the VCC has start ramping up and crosses the VPORR threshold:

  • First, the on-chip OTP memory is reset.
  • Next, the device reads the data from OTP memory, and transfers this information to configure each macro-cell and the connection mux.
  • The third stage resets the GPIOs that are configured as inputs and then enables them.
  • After that, the LUTs are reset and become active. After LUTs, the delay cells, OSC, DFFs, latches and pipe delay are initialized.
  • After all macro-cells are initialized, the internal POR signal generated by the POR macro-cell goes from low to high.
  • The last portion of the device to be initialized are the output PINs, which transition from high impedance to active at this point.

Delay blocks will pass their inputs through to the output during the startup sequence without delaying the signal per the configuration, so a LUT added in front of the input of a DLY that ANDs the DLY input with POR will cause the input signal to not appear until the device has fully powered up.

GPIO quick charge: There is an option to connect a 2kΩ resistor in parallel to any configured pull up/pull down resistors to help inputs get to the right voltage faster, especially if there is significant capacitance. The 10kΩ, 100kΩ and 1MΩ GPIO pull up/pull down resistors are not enabled until the POR sequence is completed.

Initialization: All internal macro-cells are initialized to a low level by default. Starting from when VCC exceeds VPORR, macro-cells in the TPLD1201-Q1 are powered on and forced into a reset state.

The VREF output pin driving signal can precede POR output signal going high by 3µs to 5µs. The POR signal going high indicates the mentioned power-up sequence is complete.