SCPS304 September   2024 TPLD1201-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT Macro-Cell
        2. 7.3.3.2 3-Bit LUT Macro-Cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell
      6. 7.3.6 Selectable Frequency Oscillator
      7. 7.3.7 Analog Comparators (ACMP)
      8. 7.3.8 Voltage Reference (VREF)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Option Addendum
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

5.7 Switching Characteristics

TA = 25°C (unless otherwise noted)
PARAMETER VCC MIN TYP MAX UNIT
Digital IO
tpd Delay Digital input without Schmitt trigger to Push-pull output - Rising 1.8V ± 0.09V 34.9 ns
Digital input without Schmitt trigger to Push-pull output - Falling 30.8
Digital input without Schmitt trigger to Push-pull output - Rising 3.3V ± 0.3V 20.3
Digital input without Schmitt trigger to Push-pull output - Falling 20.7
Digital input without Schmitt trigger to Push-pull output - Rising 5V ± 0.5V 16.4
Digital input without Schmitt trigger to Push-pull output - Falling 17.7
tpd Delay Digital input with Schmitt trigger to Push-pull output - Rising 1.8V ± 0.09V 38.6 ns
Digital input with Schmitt trigger to Push-pull output - Falling 32.8
Digital input with Schmitt trigger to Push-pull output - Rising 3.3V ± 0.3V 22.6
Digital input with Schmitt trigger to Push-pull output - Falling 21.5
Digital input with Schmitt trigger to Push-pull output - Rising 5V ± 0.5V 18.3
Digital input with Schmitt trigger to Push-pull output - Falling 18.0
tpd Delay Low-voltage digital input to Push-pull output - Rising 1.8V ± 0.09V 30.5 ns
Low-voltage digital input to Push-pull output - Falling 33.3
Low-voltage digital input to Push-pull output - Rising 3.3V ± 0.3V 17.9
Low-voltage digital input to Push-pull output - Falling 22.3
Low-voltage digital input to Push-pull output - Rising 5V ± 0.5V 14.0
Low-voltage digital input to Push-pull output - Falling 19.9
tpd Delay Digital input without Schmitt trigger to Open drain NMOS output - Rising 1.8V ± 0.09V 50.6 ns
Digital input without Schmitt trigger to Open drain NMOS output - Falling 25.9
Digital input without Schmitt trigger to Open drain NMOS output - Rising 3.3V ± 0.3V 21.6
Digital input without Schmitt trigger to Open drain NMOS output - Falling 16.8
Digital input without Schmitt trigger to Open drain NMOS output - Rising 5V ± 0.5V 14.2
Digital input without Schmitt trigger to Open drain NMOS output - Falling 14.0
tpd Delay Output enable from pin, OE, Hi-Z to 1 - Rising 1.8V ± 0.09V 45.2 ns
1.8V ± 0.09V 27.7
3.3V ± 0.3V 22.7
tpd Delay Output enable from pin, OE, Hi-Z to 0 - Falling 3.3V ± 0.3V 43.2 ns
5V ± 0.5V 20.6
5V ± 0.5V 20.6
Configurable Use Logic
tpd Delay 2-bit LUT - Rising 1.8V ± 0.09V 1.14 ns
2-bit LUT - Falling 1.32
2-bit LUT - Rising 3.3V ± 0.3V 1.14
2-bit LUT - Falling 1.31
2-bit LUT - Rising 5V ± 0.5V 1.16
2-bit LUT - Falling 1.35
tpd Delay 3-bit LUT - Rising 1.8V ± 0.09V 1.31 ns
3-bit LUT - Falling 1.53
3-bit LUT - Rising 3.3V ± 0.3V 1.31
3-bit LUT - Falling 1.53
3-bit LUT - Rising 5V ± 0.5V 1.31
3-bit LUT - Falling 1.53
tpd Delay 4-bit LUT - Rising 1.8V ± 0.09V 1.53 ns
4-bit LUT - Falling 1.86
4-bit LUT - Rising 3.3V ± 0.3V 1.53
4-bit LUT - Falling 1.86
4-bit LUT - Rising 5V ± 0.5V 1.53
4-bit LUT - Falling 1.86
tpd Delay Latch with nRST/nSET - Rising 1.8V ± 0.09V 1.58 ns
Latch with nRST/nSET - Falling 1.58
Latch with nRST/nSET - Rising 3.3V ± 0.3V 1.58
Latch with nRST/nSET - Falling 1.58
Latch with nRST/nSET - Rising 5V ± 0.5V 1.58
Latch with nRST/nSET - Falling 1.58
Counter/Delay
tpd Delay CNT/DLY - Rising  1.8V ± 0.09V 2.21 ns
CNT/DLY - Falling  2.01
CNT/DLY - Rising  3.3V ± 0.3V 2.21
CNT/DLY - Falling  2.01
CNT/DLY - Rising  5V ± 0.5V 2.21
CNT/DLY - Falling  2.01
Oscillator
ferr Oscillator frequency error OSC025 kHz 1.8V ± 0.09V -5 5 %
3.3V ± 0.3V -5 5
5V ± 0.5V -5 5
ferr Oscillator frequency error OSC0 2MHz 1.8V ± 0.09V -5 5 %
3.3V ± 0.3V -5 5
5V ± 0.5V -5 5
td_osc Oscillator startup delay OSC0 25 kHz (Auto power on) 1.8V ± 0.09V 32.7 µs
3.3V ± 0.3V 33.1
5V ± 0.5V 33.4
td_osc Oscillator startup delay OSC0 2MHz (Auto power on) 1.8V ± 0.09V 4.5 µs
3.3V ± 0.3V 4.9
5V ± 0.5V 5.2
tset_osc Oscillator startup settling time OSC0 25kHz (Auto power on) 1.8V ± 0.09V 1 µs
3.3V ± 0.3V 1
5V ± 0.5V 1
tset_osc Oscillator startup settling time OSC0 2MHz (Auto power on) 1.8V ± 0.09V 7 µs
3.3V ± 0.3V 7
5V ± 0.5V 7
td_err Delay error OSC (Forced power on) 1.71V to 5.5V 0 1 CLK cycle
Programmable Filter
tpflt_pw Pulse width, 1 cell PFLT mode: (any) edge detect, edge detect output 1.8V ± 0.09V 154.0 ns
3.3V ± 0.3V 157.3
5V ± 0.5V 158.7
Pulse width, 2 cells PFLT mode: (any) edge detect, edge detect output 1.8V ± 0.09V 256.2 ns
3.3V ± 0.3V 259.7
5V ± 0.5V 260.8
Pulse width, 3 cells PFLT mode: (any) edge detect, edge detect output 1.8V ± 0.09V 356.2 ns
3.3V ± 0.3V 360.3
5V ± 0.5V 361.5
Pulse width, 4 cells PFLT mode: (any) edge detect, edge detect output 1.8V ± 0.09V 455.3 ns
3.3V ± 0.3V 459.6
5V ± 0.5V 461.4
tpflt_pd
 Delay, any cells PFLT mode: (any) edge detect, edge detect output 1.8V ± 0.09V 22.0 ns
3.3V ± 0.3V 21.4
5V ± 0.5V 21.3
tpflt_d Delay, 1 cell PFLT mode: both edge delay (shared macrocell inputs) 1.8V ± 0.09V 176.0 ns
3.3V ± 0.3V 178.7
5V ± 0.5V 180.0
Delay, 2 cells PFLT mode: both edge delay (shared macrocell inputs) 1.8V ± 0.09V 278.2 ns
3.3V ± 0.3V 281.1
5V ± 0.5V 282.1
Delay, 3 cells PFLT mode: both edge delay (shared macrocell inputs) 1.8V ± 0.09V 378.2 ns
3.3V ± 0.3V 281.7
5V ± 0.5V 382.8
Delay, 4 cells PFLT mode: both edge delay (shared macrocell inputs) 1.8V ± 0.09V 477.3 ns
3.3V ± 0.3V 481.0
5V ± 0.5V 482.7