SCPS307 October   2024 SN74AC174-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Electrical Characteristics
    3. 5.3 ESD Ratings
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Switching Characteristics
    6. 5.6 Thermal Information
    7. 5.7 Timing Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Latching Logic
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Wettable Flanks
      5. 7.3.5 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC -40°C to 125°C UNIT
MIN MAX
fCLOCK Clock frequency 1.5V 34 MHz
tW Pulse duration CLR low 1.5V 5 ns
tW Pulse duration CLK high or low 1.5V 8 ns
tSU Setup time Data before CLK↑ 1.5V 5.5 ns
tSU Setup time CLR inactive 1.5V 1.4 ns
tH Hold time Data after CLK↑ 1.5V 6.1 ns
fCLOCK Clock frequency 1.8V 45 MHz
tW Pulse duration CLR low 1.8V 3.8 ns
tW Pulse duration CLK high or low 1.8V 5 ns
tSU Setup time Data before CLK↑ 1.8V 3.6 ns
tSU Setup time CLR inactive 1.8V 0.9 ns
tH Hold time Data after CLK↑ 1.8V 4.1 ns
fCLOCK Clock frequency 2.5V 90 MHz
tW Pulse duration CLR low 2.5V 2.3 ns
tW Pulse duration CLK high or low 2.5V 3.5 ns
tSU Setup time Data before CLK↑ 2.5V 2.2 ns
tSU Setup time CLR inactive 2.5V 0.5 ns
tH Hold time Data after CLK↑ 2.5V 2.6 ns
fCLOCK Clock frequency 3.3V 110 MHz
tW Pulse duration CLR low 3.3V 1.7 ns
tW Pulse duration CLK high or low 3.3V 2.2 ns
tSU Setup time Data before CLK↑ 3.3V 1.4 ns
tSU Setup time CLR inactive 3.3V 0.5 ns
tH Hold time Data after CLK↑ 3.3V 1.9 ns
fCLOCK Clock frequency 5V 150 MHz
tW Pulse duration CLR low 5V 1.1 ns
tW Pulse duration CLK high or low 5V 1.3 ns
tSU Setup time Data before CLK↑ 5V 0.9 ns
tSU Setup time CLR inactive 5V 0.3 ns
tH Hold time Data after CLK↑ 5V 1.3 ns