SFFS032 December   2022 TLV6001-Q1 , TLV6002-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 SC70 Package
    2. 2.2 VSSOP Package
  4. 3Failure Mode Distribution (FMD)
  5.   7
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 SC70 Package
    2. 4.2 VSSOP Package

4.2 VSSOP Package

Figure 4-2 shows the TLV600x-Q1 pin diagram for the VSSOP package. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the TLV600x-Q1 data sheet.

Figure 4-2 Pin Diagram (VSSOP Package)
Table 4-6 Pin FMA for Device Pins Short-Circuited to (V-) Pin
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
OUT1 1 May cause overheating. B
IN1- 2 Input at V- is valid input, however, desired application result is unlikely. C
IN1+ 3 Input at V- is valid input, however, desired application result is unlikely. C
(V-) 4 Normal operation. D
IN2+ 5 Input at V- is valid input, however, desired application result is unlikely. C
IN2- 6 Input at V- is valid input, however, desired application result is unlikely. C
OUT2 7 May cause overheating due to output short circuit current. B
(V+) 8 Diodes from input to V+ may turn due to input signal and cause EOS. B
Table 4-7 Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
OUT1 1 Output can't be used by application. C
IN1- 2 Floating input, circuit will likely not function as expected. C
IN1+ 3 Floating input, circuit will likely not function as expected. C
(V-) 4 Lowest voltage pin will try to power internal ground via ESD diode to ground. B
IN2+ 5 Floating input, circuit will likely not function as expected. C
IN2- 6 Floating input, circuit will likely not function as expected. C
OUT2 7 Output can't be used by application. C
(V+) 8 Highest voltage pin will try to power internal ground via ESD diode to VCC. B
Table 4-8 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Description of Potential Failure Effect(s) Failure Effect Class
OUT1 1 IN1- Negative feedback, creates unity gain buffer. C
IN1- 2 IN1+ No damage to device, application circuit won't work. C
IN1+ 3 (V-) Input at V- is valid input, however, desired application result is unlikely. C
(V-) 4 IN2+ Input at V- is valid input, however, desired application result is unlikely. C
IN2+ 5 IN2- No damage to device, application circuit won't work. C
IN2- 6 OUT2 Negative feedback, creates unity gain buffer. C
OUT2 7 (V+) May cause overheating. B
(V+) 8 OUT1 May cause overheating. B
Table 4-9 Pin FMA for Device Pins Short-Circuited to (V+)
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
OUT1 1 May cause overheating. B
IN1- 2 Input at V+ is valid input, however, desired application result is unlikely. C
IN1+ 3 Input at V+ is valid input, however, desired application result is unlikely. C
(V-) 4 Diodes from input to V- may turn due to input signal and cause EOS. B
IN2+ 5 Input at V+ is valid input, however, desired application result is unlikely. C
IN2- 6 Input at V+ is valid input, however, desired application result is unlikely. C
OUT2 7 May cause overheating. B
(V+) 8 Diodes from input to V+ may turn due to input signal and cause EOS. D