This document contains information for TMCS1100-Q1 (SOIC-8 package) to aid in a functional safety system design. Information provided are:
Figure 1-1 shows the device functional block diagram for reference.
The was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.
ADVANCE INFORMATION for preproduction products; subject to change without notice.
This section provides Functional Safety Failure In Time (FIT) rates for TMCS1100-Q1 based on two different industry-wide used reliability standards:
FIT IEC TR 62380 / ISO 26262 | FIT (Failures Per 109 Hours) |
---|---|
Total Component FIT Rate | 18 |
Die FIT Rate | 9 |
Package FIT Rate | 9 |
The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:
Table | Category | Reference FIT Rate | Reference Virtual TJ |
---|---|---|---|
5 | CMOS/BICMOS ASICs Analog & Mixed =<50V supply | 25 FIT | 55°C |
The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.
The failure mode distribution estimation for TMCS1100-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
Die Failure Modes | Failure Mode Distribution (%) |
---|---|
OUT open (High-Z) | 25% |
OUT to GND | 20% |
OUT to VS | 20% |
OUT functional, not in specification | 35% |
The FMD in Table 3-1 excludes short circuit faults across the isolation barrier. Faults for short circuit across the isolation barrier can be excluded according to ISO 61800-5-2:2016 if the following requirements are fulfilled:
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.
This section provides a Failure Mode Analysis (FMA) for the pins of the TMCS1100-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Class | Failure Effects |
---|---|
A | Potential device damage that affects functionality |
B | No device damage, but loss of functionality |
C | No device damage, but performance degradation |
D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the TMCS1100-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TMCS1100-Q1 data sheet.
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
IN+ | 1 | For forward current, hall-sensor bypassed, providing no signal to be sensed and amplified. If IN+ is at a large potential above GND, this will result in a lot of current being sunk. Depending upon layout and configuration, this could damage the input current system supply, the load device, or the TMCS1100. | A |
IN+ | 2 | For forward current, hall-sensor bypassed, providing no signal to be sensed and amplified. If IN+ is at a large potential above GND, this will result in a lot of current being sunk. Depending upon layout and configuration, this could damage the input current system supply, the load device, or the TMCS1100. | A |
IN- | 3 | For reverse current, hall-sensor bypassed, providing no signal to be sensed and amplified. If IN- is at a large potential above GND, this will result in a lot of current being sunk. Depending upon layout and configuration, this could damage the input current system supply, the load device, or the TMCS1100. | A |
IN- | 4 | For reverse current, hall-sensor bypassed, providing no signal to be sensed and amplified. If IN- is at a large potential above GND, this will result in a lot of current being sunk. Depending upon layout and configuration, this could damage the input current system supply, the load device, or the TMCS1100. | A |
GND | 5 | Normal Operation | D |
VREF | 6 | If intended connection is anything other than GND, functionality will be affected. | D if VREF=GND; C otherwise |
VOUT | 7 | 'Output will be pulled to GND and output current will be short circuit limited. When left in this configuration while VS connected to a high load capable supply and for certain high load conditions through the IN+ and IN- pins, die temperature could approach or exceed 150°C. | B |
VS | 8 | Power supply shorted to ground | B |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
IN+ | 1 | If left open and pin 2 is connected, pin 2 could suffer thermal stress for currents approaching SOA boundary ratings. For normal operating conditions, sensitivity error may increase. | A |
IN+ | 2 | If left open and pin 1 is connected, pin 1 could suffer thermal stress for currents approaching SOA boundary ratings. For normal operating conditions, sensitivity error may increase. | A |
IN- | 3 | If left open and pin 4 is connected, pin 4 could suffer thermal stress for currents approaching SOA boundary ratings. For normal operating conditions, sensitivity error may increase. | A |
IN- | 4 | If left open and pin 3 is connected, pin 3 could suffer thermal stress for currents approaching SOA boundary ratings. For normal operating conditions, sensitivity error may increase. | A |
GND | 5 | GND is floating. Output will be incorrect as it is no longer referenced to GND. | B |
VREF | 6 | REF will float to an unknown value. REF is incorrect and output is incorrect. | C |
VOUT | 7 | Output will be present at the pin; having no loading will not affect the output. However, the user will see unpredictable results further down on the signal chain. | B |
VS | 8 | No power to device. VOUT will stay at GND. | B |
Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|---|
IN+ | 1 | 2 - IN+ | Normal Operation. | D |
IN+ | 2 | 3 - IN- | IN+ shorted to IN-. This creates a current divider which increase sensitivity error inversely proportional to the resistance of the short. | C |
IN- | 3 | 4 - IN- | Normal Operation. | D |
IN- | 4 | 5 - GND | For reverse current, hall-sensor bypassed, providing no signal to be sensed and amplified. If IN- is at a large potential above GND, this will result in a lot of current being sunk. Depending upon layout and configuration, this could damage the input current system supply, the load device, or the TMCS1100. | A |
GND | 5 | 6 - VREF | If VREF intended connection is anything other than GND, functionality will be affected. | D if VREF=GND; C otherwise |
VREF | 6 | 7 - VOUT | Output will be pulled to VREF and output current will be short circuit limited. When left in this configuration while VREF connected to a high load capable supply and for certain high load conditions through the IN+ and IN- pins, die temperature could approach or exceed 150°C. | B |
VOUT | 7 | 8 - VS | Output will be pulled to VS and output current will be short circuit limited. When left in this configuration while VS connected to a high load capable supply and for certain high load conditions through the IN+ and IN- pins, die temperature could approach or exceed 150°C. | B |
VS | 8 | 1 - IN+ | If 6V>IN+ > 5.5V, device will be operating in non-linear range. If IN+>6V, the device will be damaged. If IN+ < Vs, a lot of current may be pulled from the stage supplying the TMCS1100 | A |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
IN+ | 1 | If 6V>IN+ > 5.5V, device will be operating in non-linear range. If IN+>6V, the device will be damaged. If IN+ < Vs, a lot of current may be pulled from the stage supplying the TMCS1100. | A |
IN+ | 2 | If 6V>IN+ > 5.5V, device will be operating in non-linear range. If IN+>6V, the device will be damaged. If IN+ < Vs, a lot of current may be pulled from the stage supplying the TMCS1100. | A |
IN- | 3 | If 6V>IN- > 5.5V, device will be operating in non-linear range. If IN->6V, the device will be damaged. If IN- < Vs, a lot of current may be pulled from the stage supplying the TMCS1100. | A |
IN- | 4 | If 6V>IN- > 5.5V, device will be operating in non-linear range. If IN->6V, the device will be damaged. If IN- < Vs, a lot of current may be pulled from the stage supplying the TMCS1100. | A |
GND | 5 | Output shorts to supply. Stage supplying the TMCS1100 will pull a lot of current | B |
VREF | 6 | Output will rail to supply and only reverse current will be measurable | D if REF=VS by design; C otherwise |
VOUT | 7 | Output will be pulled to VS and output current will be short circuit limited. When left in this configuration while VS connected to a high load capable supply and for certain high load conditions through the IN+ and IN- pins, die temperature could approach or exceed 150°C. | B |
VS | 8 | Normal operation | D |
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