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This document contains information for TLV840-Q1 (DBV package) to aid in a functional safety system design. Information provided are:
Figure 1-1 shows the device functional block diagram for reference.
TLV840-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.
This section provides Functional Safety Failure In Time (FIT) rates for TLV840-Q1 based on two different industry-wide used reliability standards:
FIT IEC TR 62380 / ISO 26262 | FIT (Failures Per 109 Hours) |
---|---|
Total Component FIT Rate | 4 |
Die FIT Rate | 2 |
Package FIT Rate | 2 |
The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:
TABLE | CATEGORY | REFERENCE FIT RATE | REFERENCE VIRTUAL TJ |
---|---|---|---|
5 | CMOS,
BICMOS Digital, analog / mixed | 25 FIT | 55°C |
The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.
The failure mode distribution estimation for TLV840-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
DIE FAILURE MODES | FAILURE MODE DISTRIBUTION (%) |
---|---|
RESET (RESET) fails to trip | 33% |
RESET (RESET) false trip | 33% |
RESET (RESET) trip outside time specification | 33% |
Pin to Pin short any two pins | 1% |
The FMD in Table 3-1 excludes short circuit faults across the isolation barrier. Faults for short circuit across the isolation barrier can be excluded according to ISO 61800-5-2:2016 if the following requirements are fulfilled:
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.
This section provides a Failure Mode Analysis (FMA) for the pins of the TLV840-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
CLASS | FAILURE EFFECTS |
---|---|
A | Potential device damage that affects functionality |
B | No device damage, but loss of functionality |
C | No device damage, but performance degradation |
D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the TLV840-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TLV840-Q1 data sheet.
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
PIN NAME | PIN NO. | DESCRIPTION OF POTENTIAL FAILURE EFFECT(S) | FAILURE EFFECT CLASS |
---|---|---|---|
RESET (open drain) |
1 | No damage to device, can affect functionality. Forces RESET to be asserted. Increased leakage current. | B |
RESET (push-pull) |
1 | Might damage the device, can affect functionality. Forces RESET to be asserted. Increased leakage current. | A |
VDD | 2 | No damage to device, can affect functionality. Shorts voltage supply to ground, increases current. | C |
GND | 3 | Normal operation. | D |
MR | 4 | Defined operation, no damage to device. Forces RESET to be asserted. | C |
CT | 5 | No damage to device, can affect functionality. Forces RESET to be asserted. | B |
PIN NAME | PIN NO. | DESCRIPTION OF POTENTIAL FAILURE EFFECT(S) | FAILURE EFFECT CLASS |
---|---|---|---|
RESET (open drain) |
1 | Reset functionality will be lost | B |
RESET (push-pull) |
1 | Reset functionality will be lost | B |
VDD | 2 | No damage to device, can affect functionality. Device is unpowered. | B |
GND | 3 | No damage to device, can affect functionality. Device is unpowered. | C |
MR | 4 | Normal operation. | D |
CT | 5 | Normal operation. | D |
PIN NAME | PIN NO. | SHORTED TO | DESCRIPTION OF POTENTIAL FAILURE EFFECT(S) | FAILURE EFFECT CLASS |
---|---|---|---|---|
RESET (open drain) |
1 | VDD | Might damage the device, can affect functionality. Forces RESET to be asserted. Increased leakage current. | A |
RESET (push-pull) |
1 | VDD | Might damage the device, can affect functionality. Forces RESET to be asserted. Increased leakage current. | A |
VDD | 2 | GND | No damage to device, can affect functionality. Shorts voltage supply to ground, increases current. | C |
GND | 3 | MR | Defined operation, no damage to device. Forces RESET to be asserted. | C |
MR | 4 | CT | Normal operation | D |
CT | 5 | RESET (open drain) | No damage to device, can affect performance. RESET does not pull high | C |
CT | 5 | RESET (push-pull) | No damage to device, can affect performance. RESET does not pull high | C |
PIN NAME | PIN NO. | DESCRIPTION OF POTENTIAL FAILURE EFFECT(S) | FAILURE EFFECT CLASS |
---|---|---|---|
RESET (open - drain) |
1 | Might damage the device, can affect functionality. Forces RESET to be asserted. Increased leakage current. | A |
RESET (push - pull) |
1 | Might damage the device, affects functionality. Increased leakage current. | A |
VDD | 2 | Normal operation. | D |
GND | 3 | No damage to device, can affect functionality. Shorts voltage supply to ground, increases current. | C |
MR | 4 | Normal operation | D |
MR (connected to GPIO or switch) | 4 | Affects functionality. Pin can't be shorted to GND or pulled low to assert RESET | B |
CT | 5 | No effect however, can affect functionality if in use. No delay in RESET. | D |
CT (connected to a capacitor) | 5 | Lost of RESET functionality. | B |