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This document contains information for REF20-Q1 (DDC package) to aid in a functional safety system design. Information provided are:
Figure 1-1 shows the device functional block diagram for reference.
REF20-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.
This section provides Functional Safety Failure In Time (FIT) rates for REF20-Q1 based on two different industry-wide used reliability standards:
FIT IEC TR 62380 / ISO 26262 | FIT (Failures Per 109 Hours) |
---|---|
Total Component FIT Rate | 5 |
Die FIT Rate | 3 |
Package FIT Rate | 2 |
The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:
TABLE | CATEGORY | REFERENCE FIT RATE | REFERENCE VIRTUAL TJ |
---|---|---|---|
5 | CMOS,
BICMOS Digital, analog / mixed | 20 FIT | 55°C |
The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.
The failure mode distribution estimation for REF20-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
DIE FAILURE MODES | FAILURE MODE DISTRIBUTION (%) |
---|---|
Output is stuck (high or low) | 20 % |
Output is floating | 20 % |
Incorrect output voltage | 20 % |
Supply current higher than specification | 15 % |
Incorrect start-up time | 10 % |
Oscillations at output | 10 % |
Temperature coefficient violates specification | 5 % |
This section provides a Failure Mode Analysis (FMA) for the pins of the REF20-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
CLASS | FAILURE EFFECTS |
---|---|
A | Potential device damage that affects functionality |
B | No device damage, but loss of functionality |
C | No device damage, but performance degradation |
D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the REF20-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the REF20-Q1data sheet.
Unless otherwise specified, it is assumed that the voltages applied to all the pins are within the Recommended Operating Range specified in the datasheet.
PIN NAME | PIN NO. | DESCRIPTION OF POTENTIAL FAILURE EFFECT(S) | FAILURE EFFECT CLASS |
---|---|---|---|
VBIAS | 1 | Might damage the device, can affect functionality. Forces short circuit current to flow through device. | A |
GND | 2 | Normal operation. | D |
EN | 3 | No device damage. Device output will be disabled. System current may increase. | B |
VIN | 4 | No device damage. Device will not generate output. Increased system current. | B |
VREF | 5 | Might damage the device, can affect functionality. Forces short circuit current to flow through device. | A |
PIN NAME | PIN NO. | DESCRIPTION OF POTENTIAL FAILURE EFFECT(S) | FAILURE EFFECT CLASS |
---|---|---|---|
VBIAS | 1 | No bias output voltage. | B |
GND | 2 | No output voltage. | B |
EN | 3 | No damage to device, can affect functionality. | B |
VIN | 4 | Device is unpowered. | B |
VREF | 5 | No reference output voltage. | B |
PIN NAME | PIN NO. | SHORTED TO | DESCRIPTION OF POTENTIAL FAILURE EFFECT(S) | FAILURE EFFECT CLASS |
---|---|---|---|---|
VBIAS | 1 | GND | Might damage the device, can affect functionality. Forces short circuit current to flow through device. | A |
GND | 2 | EN | No device damage. Device output will be disabled. | B |
EN | 3 | VIN | No damage to device. Device disable functionality will be lost. System current may increase. | B |
VIN | 4 | VREF | Might damage the device. High current flow into the reference output. | A |
VREF | 5 | VBIAS | Might damage the device. High current will flow from reference output to bias output. | A |
PIN NAME | PIN NO. | DESCRIPTION OF POTENTIAL FAILURE EFFECT(S) | FAILURE EFFECT CLASS |
---|---|---|---|
VBIAS | 1 | Might damage the device. High current flow into the bias output. | A |
GND | 2 | No device damage. Device will not generate output. Increased system current. | B |
EN | 3 | No damage to device. Device disable functionality will be lost. System current may increase. | B |
VIN | 4 | Normal operation. | D |
VREF | 5 | Might damage the device. High current flow into the bias output. | A |