SFFS188A September   2021  – June 2024 LM64440-Q1 , LM64460-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
  7. 5Revision History

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the LM644X0-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to Ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
Class Failure Effects
A Potential device damage that affects functionality
B No device damage, but loss of functionality
C No device damage, but performance degradation
D No device damage, no impact to functionality or performance

Figure 4-1 shows the LM644X0-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LM644X0-Q1 data sheet.

Pin Diagram Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
CBOOT 1 VOUT = 0V B
NC 2 No effect D
BIAS 3 Normal Operation, Chip power now from VIN causing decreased efficiency C
VCC 4 VOUT = 0V B
FB 5

VOUT >> than programmed output voltage

 B
PGOOD 6

PGOOD not valid signal. No other changes to chip performance. VOUT in regulation

 C
MODE/SYNC 7 AUTO mode operation only, VOUT normal C
EN 8 VOUT = 0V B
NC 9 No effect D
VIN2 10 VOUT = 0V B
NC 11 No effect D
PGND2 12 No effect D
NC 13 No effect D
SW1 14 Damage to HS FET A
SW2 15 Damage to HS FET A
SW3 16 Damage to HS FET A
NC 17 No effect D
PGND1 18 No effect D
NC 19 No effect D
VIN1 20 VOUT = 0V B
NC 21 No effect D
SW4 22 Damage to HS FET A
GND DAP No effect D
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
CBOOT 1 VOUT = 0V B
NC 2 No effect D
BIAS 3 Normal Operation, Chip power now from VIN causing decreased efficiency C
VCC 4

VCC output is unstable and can increase above 5.5V rating of VCC pin

 A
FB 5

VOUT >> than programmed output voltage.

 B
PGOOD 6

PGOOD not valid signal. VOUT in regulation

 C
MODE/SYNC 7 AUTO vs FPWM and spread spectrum operation undetermined, VOUT normal C
EN 8 Unpredictable operation B
NC 9 No effect D
VIN2 10

VOUT normal. Current loop is affected, potentially affecting noise/jitter/EMI/reliability

 C
NC 11 No effect D
PGND2 12 VOUT normal. Current loop is affected, potentially affecting noise/jitter/EMI/reliability C
NC 13 No effect D
SW1 14 No effect, 2 SW pins sufficient D
SW2 15 No effect, 2 SW pins sufficient D
SW3 16 No effect, 2 SW pins sufficient D
NC 17 No effect D
PGND1 18

VOUT normal. Current loop is affected, potentially affecting noise/jitter/EMI/reliability

 C
NC 19 No effect D
VIN1 20

VOUT normal. Current loop is affected, potentially affecting noise/jitter/EMI/reliability

 C
NC 21 No effect D
SW4 22 VOUT = 0V, Needed for CBOOT B
GND DAP Load regulation degraded, thermal impedance impacted C
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Description of Potential Failure Effects Failure Effect Class
CBOOT 1 NC No effect D
NC 2 BIAS No effect D
BIAS 3 VCC

VCC ESD clamp damaged if BIAS > 5V

 A
VCC 4 FB VOUT = 0V B
FB 5 PGOOD VOUT can become >> than programmed output voltage B
PGOOD 6 MODE/SYNC FPWM mode operation only, VOUT normal C
MODE/SYNC 7 EN FPWM mode operation only, VOUT normal C
EN 8 NC No effect D
NC 9 VIN2 No effect D
VIN2 10 NC No effect D
NC 11 PGND2 No effect D
PGND2 12 NC No effect D
NC 13 SW1 No effect D
SW1 14 SW2 No effect D
SW2 15 SW3 No effect D
SW3 16 NC No effect D
NC 17 PGND1 No effect D
PGND1 18 NC No effect D
NC 19 VIN1 No effect D
VIN1 20 NC No effect D
NC 21 SW4 No effect D
SW4 22 CBOOT VOUT = 0V B
GND DAP Any Other pin is shorted to ground, see Table 4-2
Table 4-5 Pin FMA for Device Pins Short-Circuited to supply
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
CBOOT 1

VOUT = 0V. CBOOT ESD clamp runs current to destruction.

 A
NC 2 No effect D
BIAS 3

If VIN exceeds 16V damage occurs. If below, normal operation

 A
VCC 4

If VIN exceeds 5.5V damage occurs.

 A
FB 5

If VIN exceeds 16V damage occurs. VOUT = 0V

 A
PGOOD 6

VOUT = 0V. PGOOD ESD clamp runs current to destruction

 A
MODE/SYNC 7 Runs in FPWM mode C
EN 8 VOUT normal D
NC 9 No effect D
VIN2 10 No effect D
NC 11 No effect D
PGND2 12 VOUT = 0V B
NC 13 No effect D
SW1 14 Damage to LS FET A
SW2 15 Damage to LS FET A
SW3 16 Damage to LS FET A
NC 17 No effect D
PGND1 18 VOUT = 0V B
NC 19 No effect D
VIN1 20 No effect D
NC 21 No effect D
SW4 22 Damage to LS FET A
GND DAP

VOUT = 0V

 B