SFFS203 September 2022 TLV1812 , TLV1822
The failure mode distribution estimation for TLV1812 and TLV1822 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
Die Failure Modes | Failure Mode Distribution (%) |
---|---|
OUT
Open (HIZ) |
15% |
OUT
Saturate high |
25% |
OUT
Saturate low |
25% |
OUT
Functional not in specification |
30% |
Short
Circuit any two pins |
5% |
The FMD in Table 3-1 excludes short circuit faults across the isolation barrier. Faults for short circuit across the isolation barrier can be excluded according to ISO 61800-5-2:2016 if the following requirements are fulfilled:
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.