SFFS231B August 2021 – July 2022 TLV3601-Q1 , TLV3602-Q1
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This document contains information for TLV3601-Q1 (DCK and DBV packages) and TLV3602-Q1 (DGK and DSG packages) to aid in a functional safety system design. Information provided are:
Figure 1-1 shows the device functional block diagram of single channel for reference.
TLV3601-Q1 and TLV3602-Q1 were developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.
ADVANCE INFORMATION for preproduction products; subject to change without notice.
This section provides Functional Safety Failure In Time (FIT) rates for the DCK and DBV packages of TLV3601-Q1 and DGK and DSG packages of TLV3602-Q1 based on two different industry-wide used reliability standards:
FIT IEC TR 62380 / ISO 26262 | DCK FIT (Failures Per 109 Hours) | DBV FIT (Failures Per 109 Hours) |
---|---|---|
Total Component FIT Rate |
3 |
4 |
Die FIT Rate | 2 | 2 |
Package FIT Rate |
1 |
2 |
FIT IEC TR 62380 / ISO 26262 | DGK FIT (Failures Per 109 Hours) | DBV FIT (Failures Per 109 Hours) |
---|---|---|
Total Component FIT Rate |
7 |
4 |
Die FIT Rate | 3 | 2 |
Package FIT Rate |
4 |
2 |
The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:
Table | Category | Reference FIT Rate | Reference Virtual TJ |
---|---|---|---|
4 | CMOS, BICMOS Digital, analog / mixed | 12 FIT | 55°C |
The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-3 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.
The failure mode distribution estimation for TLV3601-Q1 and TLV3602-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
Die Failure Modes | Failure Mode Distribution (%) |
---|---|
OUT Open (HIZ) | 15% |
OUT Saturate high | 25% |
OUT Saturate low | 25% |
OUT Functional not in specification | 30% |
Short Circuit any two pins | 5% |
The FMD in Table 3-1 excludes short circuit faults across the isolation barrier. Faults for short circuit across the isolation barrier can be excluded according to ISO 61800-5-2:2016 if the following requirements are fulfilled:
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.