SFFS257 August 2021 TPSM5601R5
The failure mode distribution estimation for TPSM5601R5 and TPSM5601R5S in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
| No Output Voltage | 60% |
| Output not in specification - voltage or timing | 25% |
| Gate driver stuck on | 5% |
| Power Good - False trip or fails to trip | 5% |
| Short circuit any two pins | 5% |