All trademarks are the property of their respective owners.
This document contains information for the INA301-Q1 (in VSSOP-8 package) to aid in a functional safety system design. Information provided are:
Figure 1-1 shows the device functional block diagram for reference.
The INA301-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.
This section provides Functional Safety Failure In Time (FIT) rates for the INA301-Q1 based on two different industry-wide used reliability standards:
FIT IEC TR 62380 / ISO 26262 | FIT (Failures Per 109 Hours) |
---|---|
Total Component FIT Rate | 7 |
Die FIT Rate | 3 |
Package FIT Rate | 4 |
The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:
Table | Category | Reference FIT Rate | Reference Virtual TJ |
---|---|---|---|
4 | BICMOS Op Amp, Comparators, Voltage Monitors | 8 FIT | 45°C |
The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.
The failure mode distribution estimation for the INA301-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
Die Failure Modes | Failure Mode Distribution (%) |
---|---|
VOUT open (Hi-Z) | 10% |
VOUT Stuck (High/Low) | 25% |
VOUT functional, not in specification | 30% |
ALERT false trip, failure to trip | 35% |
This section provides a Failure Mode Analysis (FMA) for the pins of the INA301-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Class | Failure Effects |
---|---|
A | Potential device damage that affects functionality |
B | No device damage, but loss of functionality |
C | No device damage, but performance degradation |
D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the INA301-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the INA301-Q1 data sheet.
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
VS | 1 | Power supply shorted to ground. | B |
OUT | 2 | Output shorts to ground. When left in this configuration for a long time, under high supplies self heating could cause dice junction temperature to exceed 150 degrees Celsius. | B |
LIMIT | 3 | ALERT output is stuck low. | B |
GND | 4 | Normal Operation. | D |
RESET | 5 | If intended connection is not GND, functionality will be affected. | D if RESET=GND by design; C otherwise |
ALERT | 6 | ALERT output is stuck low. | B |
IN- | 7 | In high-side configuration, a short from the bus supply to GND will occur. High current will flow from bus supply to ground. In low-side configuration, normal operation. | B for high-side or D for low-side |
IN+ | 8 | In high-side configuration, a short from the bus supply to GND will occur. High current will flow from bus supply to ground. In low side configuration, input pins are shorted. | B |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
VS | 1 | No power supply to device. Device may be biased through inputs. Output will be close to GND. | B |
OUT | 2 | Output can be left open, there is no effect on the IC. | D |
LIMIT | 3 | Comparator threshold is not defined. | B |
GND | 4 | Output will be incorrect as it is no longer referenced to GND. | B |
RESET | 5 | Comparator mode is not defined. | B |
ALERT | 6 | Pin can be left open if not needed. | D |
IN- | 7 | Differential input voltage is not well defined. | B |
IN+ | 8 | Differential input voltage is not well defined. | B |
Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|---|
VS | 1 | OUT | Output shorts to supply. When left in this configuration for a long time, under high supplies self heating could cause dice junction temperature to exceed 150 degrees Celsius. | B |
OUT | 2 | LIMIT | Comparator output will be unpredictable. | B |
LIMIT | 3 | GND | ALERT output is stuck low. | B |
GND | 4 | RESET | If intended connection is not GND, functionality will be affected. | D if RESET=GND by design; C otherwise |
RESET | 5 | ALERT | ALERT Comparator output will be unpredictable. | B |
ALERT | 6 | IN- | In low-side configuration, ALERT output is stuck low; In high-side configuration, device damage is possible. | C for low-side; A for high-side |
IN- | 7 | IN+ | Input differential voltage=0V. | C |
IN+ | 8 | VS | In high-side configuration, a short from the bus supply to VS will occur. High current will flow from bus supply to VS or vice versa. Device could be damaged. | A |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
VS | 1 | Normal operation. | D |
OUT | 2 | Output shorts to supply. When left in this configuration for a long time, under high supplies self heating could cause dice junction temperature to exceed 150 degrees Celsius. | B |
LIMIT | 3 | ALERT is stuck high or unpredictable. | B |
GND | 4 | Power supply shorted to GND. | B |
RESET | 5 | Comparator1 in Latch mode. | D if RESET=VS by design; C otherwise |
ALERT | 6 | ALERTis stuck high. Power supply could be shorted to GND though this pin. | A |
IN- | 7 | In high-side configuration, a short from the bus supply to VS will occur. High current will flow from bus supply to VS or vice versa. Device could be damaged. | A for High side or B for low side |
IN+ | 8 | In high-side configuration, a short from the bus supply to VS will occur. High current will flow from bus supply to VS or vice versa. Device could be damaged. | A for High side or B for low side |
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. |
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. |
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. |
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated |