SFFS276A September 2021 – January 2023 XTR111
4.1 HVSSOP Package
Figure 4-1 shows the XTR111 pin diagram for the HVSSOP package. For a detailed description of the device pins, see the Pin Configuration and Functions section in the XTR111 data sheet.
Figure 4-1 Pin Diagram (HVSSOP) PackageTable 4-2 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| VSP | 1 | The device supplies are shorted together, leaving the VSP pin at some voltage between the VSP and GND sources (depending on source impedance). | A |
| IS | 2 | If the supply voltage is greater than 6.5 V, and the pin is not current limited to 50 mA, the device will be damaged. | A |
| VG | 3 | If the supply voltage is greater than 18 V, and the pin is not current limited to 25 mA, the device will be damaged. Additionally, the external FET and BJT will have a low voltage at the respective gate or collector. This low voltage causes erroneous or stuck device output current due to high VGS voltage, which could theoretically damage the external FET. | A |
| REGS | 4 | The regulator voltage will be near the rail voltage, disrupting downstream circuitry that is powered from REGF. | B |
| REGF | 5 | The internal amplifier will try to force current through the short, maxing out at 15 mA to 25 mA. | B |
| VIN | 6 | The internal amplifier will rail out, completely disrupting the internal feedback mechanism, and result in erroneous output of device (stuck at 0 mA). | B |
| SET | 7 | Internal op-amp pins will be held apart, resulting in the op amp railing gate being driven high, and thus attempt to force more current out of the SET pin. This configuration completely disrupts the internal feedback mechanism, and results in erroneous output of device. | B |
| EF | 8 | The error flag will be stuck at low, meaning if read, the error flag will always indicate an error (such as a wire break) even if the device is actually working fine. | B |
| OD | 9 | The output will be stuck at enabled, meaning the output can no longer be disabled. | B |
Table 4-3 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| VSP | 1 | Device positive supply will float, potentially resulting in damage if external voltages are present at the device inputs. | A |
| IS | 2 | The external FET and BJT will not have any voltage at the respective source or emitter, giving no proper current path, and thus disrupting device output current. | B |
| VG | 3 | Pin voltage will likely drift up to the VSP rail. The external FET and BJT will have high voltage at the respective gate or collector, causing erroneous or stuck device output current due to a low VGS voltage. Capacitive coupling to this open pin could cause oscillations in the device output. | B |
| REGS | 4 | Capacitive coupling to this open pin could cause oscillations in the device regulator output, disrupting any downstream circuitry that is powered from REGF. The pin voltage will probably float to one rail or the other. | B |
| REGF | 5 | Downstream circuitry will not be powered, which could cause erroneous circuit behavior. | B |
| VIN | 6 | Capacitive coupling to this open pin could cause oscillations in the gate drive output, which could in turn cause oscillations in the device output. | B |
| SET | 7 | With no path to GND other than through the inverting input, the internal op amp will rail to shut off the internal FET, completely disrupting the internal feedback mechanism, and result in erroneous output of device. | B |
| EF | 8 | If the EF pin is open and not connected to an external pullup resistor and monitoring circuitry, to that external circuit, the error flag will appear to be stuck at high. Therefore, if the device enters a state where an error is present (such as a wire break), the monitor circuit will not detect this error. | B |
| OD | 9 | The output will be stuck at disabled because of the internal pullup resistor on the OD pin, preventing the device output from being enabled. Possibility of glitches if a 4-µA internal pullup resistor is overpowered by capacitive coupling. | B |
| GND | 10 | The device negative supply will float, potentially resulting in damage if external voltages are present at the inputs. | A |
| PAD | P | The device will not be able to thermally dissipate and could overheat with high currents. Long-term reliability and structural integrity could be compromised. | A |
Table 4-4 Pin FMA for Device Pins
Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| VSP | 1 | 2 | The external FET and BJT will have higher voltage at the respective source or emitter than intended, causing erroneous device output current due to an incorrect VGS voltage. | B |
| IS | 2 | 3 | The external FET and BJT will have the same voltage at the respective source or emitter as at the gate or collector, causing erroneous or stuck device output current due to a zero VGS voltage. | B |
| VG | 3 | 4 | The regulator voltage will be disrupted. If the resistor divider used to set REGF uses low-value resistors, VG can become loaded, resulting in an erroneous gate drive. | B |
| REGS | 4 | 5 | The internal regulator acts as a buffer of the internal 3-V reference, which will lead to an incorrect REGF output voltage. | B |
| VIN | 6 | 7 | The amplifier inputs will be shorted out, so the amplifier will rail either high or low, leading to erroneous or stuck device output. | B |
| SET | 7 | 8 | The SET resistor acts as a pulldown resistor on the EF pin, possibly forming a resistor divider that disrupts EF functionality. The internal pullup resistor on EF forces some current through the SET resistor, causing a slight error in the output current of the device. | B |
| EF | 8 | 9 | If an external pullup resistor is used on the EF pin, this pullup resistor will fight any external pulldown resistor present on the OD pin, possibly forming a voltage divider that will cause a voltage at OD in between a true high or low. This configuration could force the output to be erroneously disabled or glitch. This configuration will also cause an in-between voltage on the EF pin, disrupting EF pin functionality. | B |
| OD | 9 | 10 | Output will be stuck at enabled, meaning that the output can no longer be disabled. | B |
| PAD | P | ALL | Same as Short to GND; see Table 4-2. | |
Table 4-5 Pin FMA for Device Pins
Short-Circuited to
Supply
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| IS | 2 | The external FET and BJT will have a higher voltage at the respective source or emitter than intended, causing erroneous device output current due to an incorrect VGS voltage. | B |
| VG | 3 | The external FET and BJT will have a high voltage at the respective gate or collector, causing erroneous or stuck device output current due to a low VGS voltage. | B |
| REGS | 4 | Regulator voltage will rail out high, disrupting the downstream circuitry, and possibly damaging the device if the device is not prepared to take a high-output voltage. | B |
| REGF | 5 | The device will be damaged because REGF is not intended to sink more than 50 µA of current. | A |
| VIN | 6 | If the supply voltage is greater than 18 V, and the pin is not current limited to 25 mA, the device will be damaged. If the supply voltage is less than 18 V, the internal amplifier will rail out, completely disrupting the internal feedback mechanism and resulting in erroneous output. | A |
| SET | 7 | If the supply voltage is greater than 14 V, and the pin is not current limited to 25 mA, the device will be damaged. If the supply voltage is less than 14 V, then the internal op amp will rail and shut off the internal FET, completely disrupting the internal feedback mechanism and resulting in erroneous output. | A |
| EF | 8 | The error flag will be stuck high, so if the device enters a state where an error is present (such as a wire break), the flag will not indicate this error. | B |
| OD | 9 | The output will be stuck at disabled, meaning that the output can no longer be enabled. | B |
| GND | 10 | Device supplies will be shorted together, leaving the GND pin at some voltage between the VSP and GND sources (depending on source impedance). | A |
| PAD | P | Device supplies will be shorted together, leaving the GND/PAD pin at some voltage between the VSP and GND sources (depending on source impedance). | A |