SFFS320 December   2021 DRV8910-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)

3 Failure Mode Distribution (FMD)

The failure mode distribution estimation for the DRV8910-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity, and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures resulting from misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure Modes Failure Mode Distribution (%)
Output is stuck LOW when commanded OFF (GND short) 11%(1)
Output is stuck HIGH when commanded OFF (VM short) 11%(1)
Output is stuck OFF when commanded LOW (Open) 14%(1)
Output is stuck OFF when commanded HIGH (Open) 14%(1)
Output ON resistance too high when commanded LOW 11%(1)
Output ON resistance too high when commanded HIGH 11%(1)
Low side slew rate too fast or too slow (high-side recirculation) 5%(1)
High side slew rate too fast or too slow (low-side recirculation) 5%(1)
Dead-time is too short 4%(1)
Incorrect SPI communication 12%
Incorrect input interpretation (nSLEEP) 1%
Incorrect nFAULT assertion 1%
(1) Divide this number by 12 for FMD of each individual OUTx pin. This device leaves 2 channels unconnected internally.

DRV8910-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.