SFFS386A april   2022  – april 2023 TPSI3050

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
  6. 5Revision History

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TPSI3050. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to Ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-2.

Table 4-1 TI Classification of Failure Effects
Class Failure Effects
A Potential device damage that affects functionality
B No device damage, but loss of functionality
C No device damage, but performance degradation
D No device damage, no impact to functionality or performance

Figure 4-1 shows the TPSI3050 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TPSI3050 data sheet.

GUID-20201201-CA0I-GFBZ-4M3G-7W82T4BSNG4M-low.svg Figure 4-1 Pin Diagram

The TPSI3050 is normally operated in one of two modes of operation for a given application: three-wire mode or two-wire mode. The Pin FMA was performed individually for each of these modes of operation in the following sections.

Three-Wire Mode

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • Device configured and operating in three-wire mode
  • Device in normal operation prior to any open or short condition being applied to the respective pin
  • EN set to a static logic low or high (VDRV asserted low or high respectively)
  • Opens or shorts occur relative to primary and secondary sides of the device and is a static event
Table 4-2 Three-Wire Mode: Pin FMA for Device Pins Short-Circuited to VSSP or VSSS
Pin Name Pin No. Ground Description of Potential Failure Effect(s) Failure Effect Class
EN 1 VSSP VDRV asserted low B
PXFR 2 VSSP Subsequent power cycles result in RPXFR selection to 7.32 kΩ, which can result in longer start-up and recovery times if different RPXFR from 7.32 kΩ was used in the application. C
VDDP 3 VSSP No power transfer. VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. If EN static is high, additional leakage current into EN pin is observed on the order of 25 mA. B
VDRV 8 VSSS If VDRV was high, VDDH and VDDM rail collapse. VDRV asserts low with active clamp enabled. If VDRV was low, no effect. B
VDDH 7 VSSS VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. B
VDDM 6 VSSS VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. B
Table 4-3 Three-Wire Mode: Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
EN 1 VDRV asserted low. EN pin has an internal resistive pulldown to VSSP. B
PXFR 2 Subsequent power cycles result in RPXFR selection to 7.32 kΩ, which can result in longer start-up and recovery times if different RPXFR from 7.32 kΩ was used in the application. C
VDDP 3 No power transfer. VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. B
VSSP 4 No power transfer. VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. B
VDRV 8 No drive to external switch. External switch gate control can float dependent upon application circuitry. B
VDDH 7 VDDH can collapse under loading or switching events. B
VDDM 6 VDDH and VDDM can collapse under loading or switching events. B
VSSS 5 Normal power transfer. VDDH and VDDM rails remain charged. VDRV follows state of EN logic level. Because VSSS is a floating ground, it cannot drive external switch. B
Table 4-4 Three-Wire Mode: Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Description of Potential Failure Effect(s) Failure Effect Class
VDDH 7 VDDM VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. B
VDRV 8 VDDH If VDRV was low, VDDH and VDDM rail collapse. VDRV remains low with active clamp enabled. If VDRV was high, no effect. B
EN 1 PXFR Subsequent power cycles result in RPXFR selection to 7.32 kΩ, which can result in longer start-up and recovery times if different RPXFR from 7.32 kΩ was used in the application. C
Table 4-5 Three-Wire Mode: Pin FMA for Device Pins Short-Circuited to VDDP
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
EN 1 For standard enable devices, VDRV asserted high. For one-shot enable devices, VDRV asserted high, then remains asserted low B
PXFR 2 Subsequent power cycles result in RPXFR selection to 7.32 kΩ, which can result in longer start-up and recovery times if different RPXFR from 7.32 kΩ was used in the application. C

Two-Wire Mode

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • Device configured and operating in two-wire mode
  • Device in normal operation prior to any open or short condition being applied to the respective pin
  • EN set to a static high (VDRV asserted high)
  • Opens or shorts occur relative to primary and secondary sides of the device and is a static event
Table 4-6 Two-Wire Mode: Pin FMA for Device Pins Short-Circuited to VSSP or VSSS
Pin Name Pin No. Ground Description of Potential Failure Effect(s) Failure Effect Class
EN 1 VSSP No power transfer. VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. B
PXFR 2 VSSP Subsequent power cycles result in RPXFR selection to 7.32 kΩ, which can result in longer start-up and recovery times if different RPXFR from 7.32 kΩ was used in the application. C
VDDP 3 VSSP No power transfer. VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. Additional leakage current into EN pin will be observed on the order of 25 mA. B
VDRV 8 VSSS VDDH and VDDM rail collapse. VDRV asserts low with active clamp enabled. B
VDDH 7 VSSS VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. B
VDDM 6 VSSS VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. B
Table 4-7 Two-Wire Mode: Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
EN 1 No power transfer. VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. EN pin has an internal resistive pulldown to VSSP. B
PXFR 2 Subsequent power cycles result in RPXFR selection to 7.32 kΩ, which can result in longer start-up and recovery times if different RPXFR from 7.32 kΩ was used in the application. C
VDDP 3 No power transfer. VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. B
VSSP 4 No power transfer. VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. B
VDRV 8 No drive to external switch. External switch gate control can float dependent upon application circuitry. B
VDDH 7 VDDH can collapse under loading or switching events. B
VDDM 6 VDDH and VDDM can collapse under loading or switching events. B
VSSS 5 Normal power transfer. VDDH and VDDM rails remain charged. VDRV follows state of EN logic level. Because VSSS is a floating ground, it cannot drive external switch. B
Table 4-8 Two-Wire Mode: Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Description of Potential Failure Effect(s) Failure Effect Class
VDDH 7 VDDM VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. B
VDRV 8 VDDH VDRV remains high. B
EN 1 PXFR Subsequent power cycles result in RPXFR selection to 7.32 kΩ, which can result in longer start-up and recovery times if different RPXFR from 7.32 kΩ was used in the application. C
Table 4-9 Two-Wire Mode: Pin FMA for Device Pins Short-Circuited to VDDP
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
EN 1 If EN voltage exceeds absolute maximum of VDDP, potential damage of device can occur. A
PXFR 2 Subsequent power cycles result in RPXFR selection to 7.32 kΩ, which can result in longer start-up and recovery times if different RPXFR from 7.32 kΩ was used in the application. C