SFFS477 June 2022 ADS131M03-Q1
The failure mode distribution estimation for the ADS131M03-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity, and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures resulting from misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
|
Incorrect conversion result of an individual ADC(1) (for example, if the ADC output code is at positive or negative full scale, 0 V, undetermined, or is otherwise incorrect). |
40% |
| SPI communication error | 10% |
|
Register bit error leading to incorrect device configuration (device behavior depends on which user or internal register bit is affected). |
10% |
| Gain error of an individual ADC out of specification(1) | 10% |
| Offset error of an individual ADC out of specification(1) | 5% |
| Noise of the conversion result of an individual ADC out of specification(1) | 5% |
| INL of an individual ADC out of specification(1) | 5% |
|
Gain error, INL, or noise of the conversion results of all four ADCs out of specification because of common circuitry (common circuitry includes the internal supplies, voltage reference, bias current generator, and clock). |
5% |
| The ADC output code bit is stuck-at | 5% |
| Device behavior is undetermined | 5% |