SFFS573 February 2023 TLVM13610

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TLVM13610. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to Ground (see Table 4-2)
Pin open-circuited (see Table 4-3)
Pin short-circuited to an adjacent pin (see Table 4-4)
Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality
B	No device damage, but loss of functionality
C	No device damage, but performance degradation
D	No device damage, no impact to functionality or performance

#FIGURE21 shows the TLVM13610 pin diagram. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the TLVM13610 data sheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

Application circuit, as per the TLVM13610 data sheet is used.

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground

Pin Name	Pin No	Description of Potential Failure Effect(s)	Failure Effect Class
VIN	1, 18	VOUT = 0 V. Possible damage to customer input supply, PCB can occur unless customer provides protection, or both. Reverse current from the VOUT pin to VIN pin, due to discharge of output capacitors, can damage the regulator.	B
RBOOT	2	Loss of output voltage	A
BOOT	3	Driver supply to high-side MOSFET is lost. Output voltage is regulated. Possible damage to the internal regulator and CBOOT charging circuit	B
SW	4	Shorting the SW pin to ground results in large currents through the device and subsequent damage. No output voltage is produced.	A
VLDOIN	5	Normal operation, IC powers from VIN, causing decreased efficiency.	C
VCC	6	Internal circuits are disabled. No output voltage is generated. Possible increase in input current.	B
AGND	7, 11	No effect	D
FB	8	The regulator operates at maximum duty cycle. Output voltage rised to nearly the input voltage level. Possible damage to customer load, output stage components can occur, or both.	B
VOUT	9, 10	Loss of output voltage	B
RT	12	Switching frequency set to internal 2.2 MHz	C
PG	13	This is a valid connection for the PG output. PG functionality is lost.	D
AGND	14	This is a valid connection for AGND.	D
AGND	15	This is a valid connection for AGND.	D
NC	16	No effect	D
EN	17	This is a valid connection for the EN input. Enable functionality is lost; the device remains off with no output voltage generated.	B
PGND	19, 20, 21, 22	This is the recommended connection for PGND	D

Table 4-3 Pin FMA for Device Pins Open-Circuited

Pin Name	Pin No	Description of Potential Failure Effect(s)	Failure Effect Class
VIN	1,18	VOUT = 0 V.	B
RBOOT	2	Normal operation. Device uses internal 100 Ω for slowest switch-node slew rate.	D
BOOT	3	Normal operation. Device uses internal 100-nF bootstrap capacitor.	D
SW	4	Normal operation	D
VLDOIN	5	Normal operation, IC powers from VIN, causing decreased efficiency	C
VCC	6	Normal operation	D
AGND	7, 11	Load regulation degraded	C
FB	8	VOUT >> than programmed output voltage	B
VOUT	9,10	Loss of output regulation	B
RT	12	Loss of output regulation	C
PG	13	This is a valid connection for the PG output. PG functionality is lost.	D
AGND	14	May have output voltage ripple increase	C
AGND	15	Mode may switch randomly. Unpredictable behavior	C
NC	16	Valid connection	D
EN	17	Loss of enable functionality. Erratic operation; probable loss of regulation.	B
PGND	19, 20, 21, 22	Load regulation degraded, thermal impedance impacted. Loss of operation if all four pins are open.	B

Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin

Pin Name	Pin No	Shorted To	Description of Potential Failure Effect(s)	Failure Effect Class
VIN	1	RBOOT	VOUT = 0 V. Damage to low-side circuitry if PGND >> AGND	A
RBOOT	2	BOOT	VOUT normal operation	D
BOOT	3	SW	Loss of output regulation	B
SW	4	VLDOIN	If SW > 20 V, damage to VLDOIN pin	A
VLDOIN	5	VCC	If VLDO > 5 V, damage to VCC pin	A
VCC	6	AGND	Internal circuit disabled	B
AGND	7	FB	VOUT >> than programmed output voltage, regulate close to VIN	B
FB	8	VOUT	VOUT << than programmed output voltage, regulate to reference voltage	B
VOUT	9	VOUT	Valid connection	D
VOUT	10	AGND	Loss of output regulation	C
AGND	11	RT	Switching frequency set to 2.1MHz	C
RT	12	PG	If PG low, switching frequency set to 2.1 MHz. If PG high, switching frequency is set to 400 kHz.	C
PG	13	SPSP	PG low at start-up, spread spectrum is disabled.	C
AGND	14	AGND	Normal operation	D
AGND	15	NC	Normal operation	D
NC	16	EN	EN pin left floating. Loss of enable functionality. Erratic operation; probably loss of regulation.	B
EN	17	VIN	Loss of precision enable feature. Device operates normally.	D
VIN	18	VIN	Valid connection	D
PGND	19, 20, 21, 22	Any	Other pin is shorted to ground, see Table 4-2	—

Table 4-5 Pin FMA for Device Pins Short-Circuited to supply

Pin Name	Pin No	Description of Potential Failure Effect(s)	Failure Effect Class
VIN	1, 18	No effect	D
RBOOT	2	VOUT = 0 V. RBOOT ESD clamp runs current to destruction.	A
BOOT	3	VOUT = 0 V. BOOT ESD clamp runs current to destruction.	A
SW	4	Damage to low-side FET	A
VLDOIN	5	If VIN exceeds 16 V, damage occurs. If below 16 V, normal operation.	A
VCC	6	If VIN exceeds 5.5 V damage occurs.	A
AGND	7, 11	VOUT = 0 V. Damage to other pins referred to GND.	A
FB	8	If VIN exceeds 5.5 V, damage occurs. VOUT = 0 V.	A
VOUT	9, 10	Damage to low-side FET. The output voltage rises to nearly the level of VIN. Customer load is damaged. Possible damage to device.	A
RT	12	VOUT = 0 V	B
PG	13	VOUT = 0 V. PGOOD ESD clamp runs current to destruction.	A
AGND	14	May have output voltage ripple increase	D
AGND	15	Efficiency decrease in light-load	C
NC	16	No effect	D
EN	17	Loss of precision enable feature. Device operates normally.	D
PGND	19, 20, 21, 22	VOUT = 0 V. Damage to low-side circuitry if PGND >> AGND	A