SFFS586A May 2023 – November 2023 LM5171-Q1
PRODUCTION DATA
This section provides a failure mode analysis (FMA) for the pins of the LM5171-Q1 and LM5171. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-3 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Class | Failure Effects |
---|---|
A | Potential device damage that affects functionality. |
B | No device damage, but loss of functionality. |
C | No device damage, but performance degradation. |
D | No device damage, no impact to functionality or performance. |
Pin Diagram shows the LM5171-Q1/LM5171 pin diagram. For a detailed description of the device pins, see the Pin Configuration and Functions section in the LM5171-Q1/LM5171 data sheet.
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
Pin No | Pin Name | Description of Potential Failure Effect (s) | Failure Effect Class |
---|---|---|---|
1 | VREF | No switching | B |
2 | FBLV | No switching | B |
3 | ERRLV | No switching | B |
4 | IMON2 | Normal operation, but loss of CH-2 current monitor | D |
5 | CSA2 | Invalid current sense, and 12V Rail is shorted to GND | B |
6 | CSB2 | Invalid current sense, and 12V Rail is shorted to GND | B |
7 | ISET2 | Loss of current setting command in CH-2 | B |
8 | COMP2 | No switching in CH-2 | B |
9 | SS/DEM2 | No switching in CH-2 | B |
10 | EN2 | No switching in CH-2 | B |
11 | DIR2 | CH-2 can only operate in Boost Mode, no Buck Mode possible | C |
12 | VDD | Unable to startup | B |
13 | HV2 | CH-2 Unable to Startup | B |
14 | HB2 | No CH-2 high-side boot voltage; not able to run CH-2 in buck mode | B |
15 | HO2 | CH-2 high side driver may be damaged | B |
16 | SW2 | Switch Node of CH-2 grounded | B |
17 | LO2 | Overloading of the CH-2 low side driver | B |
18 | PGND | Normal operation | D |
19 | VCC | Loss of VCC bias supply. Unable to start up | B |
20 | LO1 | Overloading of the CH-1 low side driver | B |
21 | SW1 | Switch Node of CH-1 grounded | B |
22 | HO1 | CH-1 high side driver may be damaged | B |
23 | HB1 | No CH-1 high-side boot voltage; not able to run CH-1 in buck mode | B |
24 | HV1 | CH-1 Unable to Startup | B |
25 | LDODRV | Normal operation, but VCC pin must be supplied externally | D |
26 | DIR1 | CH-1 can only operate in Boost Mode, no Buck Mode possible | C |
27 | EN1 | No switching in CH-1 | B |
28 | SS/DEM1 | No switching in CH-1 | B |
29 | COMP1 | No switching in CH-1 | B |
30 | ISET1 | Loss of current setting command in CH-1 | B |
31 | CSB1 | Invalid current sense, and 12V Rail is shorted to GND | B |
32 | CSA1 | Invalid current sense, and 12V Rail is shorted to GND | B |
33 | IMON1 | Normal operation, but loss of CH-1 current monitor | D |
34 | EERHV | No switching | B |
35 | FBHV | No switching | B |
36 | OVP | Normal operation. Loss of 48V OVP in CH-1 or both channels in parallel operation | D |
37 | SDA | Normal operation but no I2C communication | D |
38 | SCL | Normal operation but no I2C communication | D |
39 | SYNCO | Normal operation, loss of synchronization for responder phases | D |
40 | SYNCI | Normal operation, loss of synchronization | D |
41 | OPT | Normal operation, loss of synchronization | D |
42 | OSC | Clock frequency is higher, unpredictable switching behavior | B |
43 | AGND | Normal operation | D |
44 | CFG | Normal operation, but current monitor only possible for Boost mode for single I2C address | D |
45 | UVLO | Unable to startup | B |
46 | DT/SD | Unable to startup | B |
47 | IPK | No switching | B |
48 | VSET | No switching | B |
Pin No | Pin Name | Description of Potential Failure Effect (s) | Failure Effect Class |
---|---|---|---|
1 | VREF | No switching | B |
2 | FBLV | No switching | B |
3 | ERRLV | No switching | B |
4 | IMON2 | Normal operation, but loss of CH-2 current monitor | D |
5 | CSA2 | Loss of CH-2 current regulation | B |
6 | CSB2 | Loss of CH-2 current regulation | B |
7 | ISET2 | Loss of current setting command in CH-2 | B |
8 | COMP2 | Loss of CH-2 loop compensation and loss of loop stability | B |
9 | SS/DEM2 | No soft-start or DEM mode operation in CH-2 | B |
10 | EN2 | No switching in CH-2 | B |
11 | DIR2 | Invalid DIR command and no switching in CH-2 | B |
12 | VDD | Normal operation can not be ensured | B |
13 | HV2 | CH-2 Unable to startup | B |
14 | HB2 | Loss of CH-2 Buck Mode Operation | C |
15 | HO2 | Loss of CH-2 Buck Mode Operation | C |
16 | SW2 | Loss of CH-2 Buck Mode Operation | C |
17 | LO2 | Loss of CH-2 Buck Mode Operation | C |
18 | PGND | No switching | B |
19 | VCC | No switching | B |
20 | LO1 | Loss of CH-1 Boost Mode Operation | C |
21 | SW1 | Loss of CH-1 Boost Mode Operation | C |
22 | HO1 | Loss of CH-1 Boost Mode Operation | C |
23 | HB1 | Loss of CH-1 Boost Mode Operation | C |
24 | HV1 | CH-1 Unable to Startup | B |
25 | LDODRV | Normal operation, but VCC pin must be supplied externally | D |
26 | DIR1 | Invalid DIR command and no switching in CH-1 | B |
27 | EN1 | No CH-1 switching | B |
28 | SS/DEM1 | No soft-start or DEM mode operation in CH-1 | B |
29 | COMP1 | Loss of CH-1 loop compensation and loss of loop stability | B |
30 | ISET1 | Loss of current setting command in CH-1 | B |
31 | CSB1 | Loss of CH-1 current regulation | B |
32 | CSA1 | Loss of CH-1 current regulation | B |
33 | IMON1 | Normal operation, but loss of CH-1 current monitor | D |
34 | EERHV | No switching | B |
35 | FBHV | No switching | B |
36 | OVP | Normal operation. Loss of 48V OVP in CH-1 or both channels in parallel operation | D |
37 | SDA | Normal operation but no I2C communication | D |
38 | SCL | Normal operation but no I2C communication | D |
39 | SYNCO | Normal operation, loss of synchronization | D |
40 | SYNCI | Normal operation, loss of synchronization | D |
41 | OPT | Normal operation, in 120 degree interleaving | D |
42 | OSC | Loss of clock function, No switching | B |
43 | AGND | Loss of analog reference ground. No switching | B |
44 | CFG | Normal operation, but loss of current monitor and I2C Interface | D |
45 | UVLO | Unable to startup | B |
46 | DT/SD | Normal switching with built-in adaptive dead time scheme | D |
47 | IPK | No switching | B |
48 | VSET | No switching | B |
Pin No | Pin Name | Description of Potential Failure Effect (s) | Failure Effect Class |
---|---|---|---|
1 | VREF | Loss of loop control and no switching activity in Buck Mode | C |
2 | FBLV | Loss of loop control and no switching activity in Buck Mode | C |
3 | ERRLV | Loss of loop control and no switching activity in Buck Mode | C |
4 | IMON2 | Pin voltage rating is exceeded and may cause pin damage when shorted to 12V rail | B |
5 | CSA2 | Loss of current sense and loss of CH-2 current regulation | B |
6 | CSB2 | Loss of current sense and loss of CH-2 current regulation | B |
7 | ISET2 | Loss of current setting command, Pin voltage rating is exceeded and may cause pin damage when shorted to CSB2 | B |
8 | COMP2 | Loop compensation may be altered by SS capacitor and causing instable operation | B |
9 | SS/DEM2 | Normal operation without soft-start or DEM mode operation in CH-1 | D |
10 | EN2 | Normal operation in Buck Mode, no Boost Mode in CH-2 | C |
11 | DIR2 | Normal operation in Buck Mode, no Boost Mode in CH-2 | C |
12 | VDD | Normal operation in Buck Mode, no Boost Mode in CH-2 | C |
13 | HV2 | No switching in CH-2 | B |
14 | HB2 | Pin voltage rating is exceeded and may cause pin damage when shorted to HV2 | B |
15 | HO2 | Pin voltage rating is exceeded and may cause pin damage when shorted to SW2 | B |
16 | SW2 | No switching in CH-2 | B |
17 | LO2 | Pin voltage rating is exceeded and may cause pin damage when shorted to HV2 | B |
18 | PGND | No switching on LO2 when LO2 is shorted to ground rail. Unable to startup when VCC rail is shorted to ground rail | B |
19 | VCC | Unable to startup when VCC rail is shorted to ground rail. No switching on LO1 when LO1 is shorted to VCC rail | B |
20 | LO1 | Pin voltage rating is exceeded and may cause pin damage when shorted to SW1 | B |
21 | SW1 | No switching in CH-1 | B |
22 | HO1 | Pin voltage rating is exceeded and may cause pin damage when shorted to SW1 | B |
23 | HB1 | Pin voltage rating is exceeded and may cause pin damage when shorted to HV1 | B |
24 | HV1 | No switching in CH-1 | B |
25 | LDODRV | Normal operation | D |
26 | DIR1 | Normal operation in Buck Mode, no Boost Mode in CH-1 when shorted to EN1, Pin voltage rating is exceeded and may cause pin damage when shorted to LDODRV | C |
27 | EN1 | Normal operation in Buck Mode, no Boost Mode in CH-1 | C |
28 | SS/DEM1 | Normal operation without soft-start or DEM mode operation in CH-1 | D |
29 | COMP1 | Loop compensation may be altered by SS capacitor and causing instable operation | B |
30 | ISET1 | Loss of current setting command, Pin voltage rating is exceeded and may cause pin damage when shorted to CSB1 | B |
31 | CSB1 | Loss of current sense and loss of CH-1 current regulation | B |
32 | CSA1 | Loss of current sense and loss of CH-1 current regulation | B |
33 | IMON1 | Normal operation with loss of CH-1 current monitor, Pin voltage rating is exceeded and may cause pin damage when shorted to CSA1 | D |
34 | EERHV | Loss of loop control and no switching activity in Boost Mode | C |
35 | FBHV | Loss of loop control and no switching activity in Boost Mode | C |
36 | OVP | Normal operation. Loss of 48V OVP in CH-1 or both channels in parallel operation | D |
37 | SDA | Normal operation but no I2C communication | D |
38 | SCL | Normal operation but no I2C communication | D |
39 | SYNCO | Normal operation, loss of synchronization | D |
40 | SYNCI | Normal operation, loss of synchronization | D |
41 | OPT | Unreliable clock interleaving may affect operation | B |
42 | OSC | Unpredictable clock function, unpredictable switching behavior | B |
43 | AGND | Unpredictable clock function, unpredictable switching behavior | B |
44 | CFG | Normal operation, but current monitor function not available | D |
45 | UVLO | Normal operation with unpredictable DT setting when shorted to DT/SD pin | D |
46 | DT/SD | Normal operation with unpredictable DT setting when shorted to DT/SD pin | D |
47 | IPK | Unreliable peak current setting and unpredictable switching behavior | B |
48 | VSET | Unpredictable switching behavior | B |