SFFS597 april 2023 TPS7B85-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a failure mode analysis (FMA) for the pins of the TPS7B85-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure
Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Figure 4-1 shows the TPS7B85-Q1 pin diagram. For a detailed description of the device pins, see the Pin Configuration and Functions section in the TPS7B85-Q1 data sheet.
Figure 4-1 Pin DiagramTable 4-2 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| OUT | 1 | Output voltage is at or near ground. The device is in current limit. The device can cycle in and out of thermal shutdown depending on power dissipation. | B |
| PGADJ | 2 | The PG threshold is set to VPG(TH,FALLING). | B |
| SO | 3 | Ground current is increased. | B |
| DELAY | 4 | Ground current is increased. | B |
| NC | 5 | No effect. Normal operation. | D |
| GND | 6 | No effect. Normal operation. | D |
| PG | 7 | Ground current is increased. | B |
| EN | 8 | The device is always off. | B |
| SI | 9 | The SO output is always low. | B |
| IN | 10 | No input to the device. The output is off. | B |
Table 4-3 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| OUT | 1 | The load is not powered. | B |
| PGADJ | 2 | PG either trips normally or trips early. The state is indeterminate. | B |
| SO | 3 | The SO output loses functionality. | B |
| DELAY | 4 | The power-good delay is t(DLY_FIX). | C |
| NC | 5 | No effect. Normal operation. | D |
| GND | 6 | There is no current loop for internal biasing, so the device cannot function. | B |
| PG | 7 | The PG output is not accessible. | B |
| EN | 8 | The device state is unknown. The device can be on or off. | B |
| SI | 9 | SO output is unreliable. Ground current can be increased if SO output is pulled low due to the floating SI input. | B |
| IN | 10 | No input. The output is at ground. | B |
Table 4-4 Pin FMA for Device Pins
Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| OUT | 1 | PGADJ | The PG output asserts at VOUT = VPGADJ(TH,FALLING) + VPGADJ(HYST). Damage is possible if VOUT exceeds the PGADJ absolute maximum rating. | B/A |
| PGADJ | 2 | SO | If SO is logic high, the PG output asserts at VOUT = VPGADJ(TH,FALLING) + VPGADJ(HYST). If SO is logic low, PG asserts at the default output voltage ratio. | B |
| SO | 3 | DELAY | If SO never asserts, PG cannot assert. If SO asserts and VOUT < DELAY (absolute maximum), the delay function is overridden and the default delay is used. Damage is possible if VOUT exceeds the DELAY absolute maximum rating. | B/A |
| DELAY | 4 | NC | No effect. Normal operation. | D |
| GND | 6 | PG | PG functionality is lost and ground current increases. | B |
| PG | 7 | EN | PG functionality is lost. If EN is pulled low by PG, the device turns off. If VEN > VOUT, the device is not loaded, and VOUT > VPG(TH,RISING), VOUT charges to VEN. Damage is possible if VEN > VPG (absolute maximum). | B/A |
| EN | 8 | SI | The device state (ON/OFF) depends on the voltage at SI, or the SI/SO circuit depends on voltage at EN, depending on which supply has a stronger driving capability to the EN and SI pins. | B |
| SI | 9 | IN | SO is always high. | B |
Table 4-5 Pin FMA for Device Pins
Short-Circuited to
Supply
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| OUT | 1 | Regulation is not possible. VOUT = VIN. | B |
| PGADJ | 2 | PG asserts after the power-good delay period has expired, causing a false power-good signal. PGADJ can be damaged if VIN exceeds the absolute maximum rating for PGADJ. | B/A |
| SO | 3 | When there is a low-load condition, VOUT can charge to VIN. SO can be damaged if VIN exceeds the absolute maximum rating for SO. | B/A |
| DELAY | 4 | There is no PG delay. PG trips when the output gets to the target with no delay. | B |
| NC | 5 | No effect. Normal operation. | D |
| GND | 6 | No input to the device. The output is off. | B |
| PG | 7 | When there is a low-load condition, VOUT can charge to VIN. SO can be damaged if VIN exceeds the absolute maximum rating for SO. | B/A |
| EN | 8 | The device is always on when VIN > VUVLO(RISING). | B |
| SI | 9 | The SO output is a function of only VIN, VSI(HIGH), and VSI(LOW). | B |
| IN | 10 | No effect. Normal operation. | D |