SFFS636 December 2024 TPS4810-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a failure mode analysis (FMA) for the pins of the TPS4810-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Figure 4-1 shows the TPS4810-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TPS4810-Q1 data sheet.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- Follow the data sheet recommendations for operating conditions, external component selection, and PCB layout
Table 4-2 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| EN/UVLO | 1 | Normal operation. The device is disabled. | B |
| INP2 | 2 | Normal operation. The G2 output is low and the external FET is off. | B |
| INP1 | 3 | Normal operation. The G1PD output is low and the external FET is off. | B |
| NC | 4 | Normal operation. | D |
| FLT | 5 | Overcurrent, UVLO, charge pump UVLO fault diagnostic cannot be reported. | B |
| GND | 6 | Normal operation. | D |
| CS_SEL | 7 | Normal operation with current sensing configured for high-side sensing. | B |
| ISCP | 8 | SCP threshold sets to minimum threshold. | B |
| TMR | 9 | Overcurrent does not get detected, hence, overcurrent protection is disabled. | B |
| SCP_TEST | 10 | Normal operation. | B |
| G2 | 11 | With G2 grounded, if the pin voltage between SRC and G2 exceeds the pin data sheet range, the exceedance causes device damage resulting from voltage breakdown on the ESD circuit. | A |
| BST | 12 | Gate driver supply does not come up. FETs remain OFF. | B |
| SRC | 13 | Short to GND protection starts. | B |
| G1PD | 14 | With G1PD grounded, if the pin voltage between SRC and G1PD exceeds the pin data sheet range, the exceedance can cause device damage resulting from voltage breakdown on the ESD circuit. | A |
| G1PU | 15 | Gate driver supply gets short circuited. FETs remain OFF. | B |
| CS- | 17 | Short to GND protection starts. | B |
| CS+ | 18 | With CS+ grounded, if the pin voltage between CS+ and CS– exceeds the pin data sheet range, the exceedance can cause device damage resulting from voltage breakdown on ESD circuit. | A |
| NC | 19 | Normal operation. | D |
| VS | 20 | Device supply is grounded. Device does not power up. | B |
Table 4-3 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| EN/UVLO | 1 | Internal pulldown brings EN/UVLO low, disabling the device. | B |
| INP2 | 2 | Internal pulldown brings INP2 low, pulling G2 output low. | B |
| INP1 | 3 | Internal pulldown brings INP1 low, pulling G1PD output low. | B |
| NC | 4 | Normal operation. | D |
| FLT | 5 | Overcurrent, UVLO, charge pump UVLO fault diagnostic cannot be reported. | B |
| GND | 6 | Device does not power up and is disabled. | B |
| CS_SEL | 7 | Internal pulldown brings CS_SEL low, resulting in normal operation with current sensing configured for high-side sensing. | B |
| ISCP | 8 | SCP threshold sets to maximum threshold. | B |
| TMR | 9 | Overcurrent response time and auto-retry duration is reduced to the minimum setting of the device. | C |
| SCP_TEST | 10 | Internal pulldown brings CS_SEL low, resulting in normal operation. | B |
| G2 | 11 | G2 output does is not controlled. | B |
| BST | 12 | External FET can be turned ON and OFF repetitively due to no capacitor connection at BST pin. | B |
| SRC | 13 | The external FET does not turn OFF as the FET source disconnects from the internal pulldown driver. | B |
| G1PD | 14 | The external FET does not turn OFF as the FET GATE disconnects from the internal pulldown driver. | B |
| G1PU | 15 | The external FET does not turn OFF as the FET GATE disconnects from the internal pulldown driver. | B |
| CS- | 17 | CS- gets internally clamped to CS+ minus 2 diode drops. If the ISCP feature is used, then the external FET potentially does not turn ON due to a false overcurrent detection. | B |
| CS+ | 18 | ISCP feature does not work. | B |
| NC | 19 | Normal operation. | D |
| VS | 20 | Device does not power up and is disabled. | B |
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| EN/UVLO | 1 | 2 (INP2) | If EN/UVLO is driven high, then INP2 is detected high, making the G2 output high. | B |
| INP2 | 2 | 3 (INP1) | If INP2 is driven high, then INP1 is detected high, making the G1PU and G2 output high. | B |
| INP1 | 3 | 4 (NC) | Normal operation. | D |
| NC | 4 | 5 (FLT) | Normal operation. | D |
| FLT | 5 | 6 (GND) | Fault deviations are not indicated. | B |
| GND | 6 | 7 (CS_SEL) | Normal operation. Device is configured for high-side sensing. | B |
| CS_SEL | 7 | 8 (ISCP) | With CS_SEL grounded, the SCP threshold sets to minimum threshold. With CS_SEL pulled high, the SCP threshold sets to maximum threshold. | C |
| ISCP | 8 | 9 (TMR) | TMR and ISCP thresholds are affected. External FET shuts off at a different threshold than set by ISCP. During an overcurrent fault the device is in latch-off mode if ISCP has a < 100kΩ resistor. | C |
| TMR | 9 | 10 (SCP_TEST) | SCP_TEST feature gets disabled. | B |
| G2 | 11 | 12 (BST) | When INP2 is driven high, BST (gate driver supply) gets loaded through the internal G2 pulldown switch. Gate driver UVLO hits result in turning off the external FETs. | B |
| BST | 12 | 13 (SRC) | Gate drive supply is shorted and external FETs do not turn ON. | B |
| SRC | 13 | 14 (G1PD) | Shorting of the pulldown switch (between G1PD and SRC) of the internal gate driver. External FET remains OFF. | B |
| G1PD | 14 | 15 (G1PU) | Turn ON and OFF speeds of the external FETs can be impacted. | C |
| CS- | 17 | 18 (CS+) | Bypasses the external current sense resistor or FET VDS sensing based on application circuit. SCP features get disabled. | B |
| CS+ | 18 | 19 (NC) | Normal operation. | D |
| NC | 19 | 20 (VS) | Normal operation. | D |
Table 4-5 Pin FMA for Device Pins
Short-Circuited to Supply
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| EN/UVLO | 1 | EN/UVLO pin is supply rated. Device remains enabled. | B |
| INP2 | 2 | INP2 pin is supply rated and is treated as driven high. | B |
| INP1 | 3 | INP1 pin is supply rated and is treated as driven high. | B |
| NC | 4 | Normal operation. | D |
| FLT | 5 | If pin voltage exceeds the pin data sheet range, the exceedance can cause device damage resulting from voltage breakdown on the ESD circuit. | A |
| GND | 6 | Supply power is bypassed and device does not turn on. | B |
| CS_SEL | 7 | CS_SEL pin is supply rated. Device is configured for low-side current sensing. | B |
| ISCP | 8 | If pin voltage exceeds the pin data sheet range, the exceedance can cause device damage resulting from voltage breakdown on the ESD circuit. | A |
| TMR | 9 | If pin voltage exceeds the pin data sheet range, the exceedance can cause device damage resulting from voltage breakdown on ESD circuit. | A |
| SCP_TEST | 10 | If pin voltage exceeds the pin data sheet range, the exceedance can cause device damage resulting from voltage breakdown on the ESD circuit. | A |
| G2 | 11 | If pin voltage exceeds the pin data sheet range, the exceedance can cause device damage resulting from voltage breakdown on the ESD circuit. | A |
| BST | 12 | If pin voltage exceeds the pin data sheet range, the exceedance can cause device damage resulting from voltage breakdown on the ESD circuit. | A |
| SRC | 13 | Output stuck onto supply. | B |
| G1PD | 14 | If pin voltage exceeds the pin data sheet range, the exceedance can cause device damage resulting from voltage breakdown on the ESD circuit. | A |
| G1PU | 15 | If pin voltage exceeds the pin data sheet range, the exceedance can cause device damage resulting from voltage breakdown on the ESD circuit. | A |
| CS- | 17 | In the application, the external sense resistor, or FET VDS sensing, is bypassed. Short circuit protection does not work. | A |
| CS+ | 18 | No effect. Normal operation. | D |
| NC | 19 | No effect. Normal operation. | D |
| VS | 20 | No effect. Normal operation. | D |