SFFS659 December 2024 DRV5056-Q1

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the DRV5056-Q1 (SOT-23 and TO-92 packages). The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to ground (see Table 4-2 and Table 4-5.)
Pin open-circuited (see Table 4-3 and Table 4-6)
Pin short-circuited to supply (see Table 4-4 and Table 4-7)

Table 4-2 through Table 4-7 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality
B	No device damage, but loss of functionality
C	No device damage, but performance degradation
D	No device damage, no impact to functionality or performance

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

External pullup resistor on CS to VDD
RC filter on every analog input, AINx.
Series resistors are sized to limit the input currents into the analog inputs to <10 mA in all circumstances (for example, in case the device is unpowered and the input signal is applied).
The device is the only slave on the SPI bus.