SFFS659 December   2024 DRV5056-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 SOT-23 Package
    2. 2.2 TO-92 Package
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 SOT-23 Package
    2. 4.2 TO-92 Package

4.2 TO-92 Package

Figure 4-2 shows the DRV5056-Q1 pin diagram for the TO-92 package. For a detailed description of the device pins, see the Pin Configuration and Functions section in the DRV5056-Q1 data sheet.

DRV5056-Q1 Pin Diagram (TO-92 Package) Figure 4-2 Pin Diagram (TO-92 Package)
Table 4-5 Pin FMA for Device Pins Short-Circuited to Ground
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
VCC 1 Supply shorted to Ground. System will source high current as a result and may current limit. Thermal damage may result. B B
GND 2 Normal Mode of operation D
OUT 3 DRV5056-Q1 will not be damaged. Output will be pulled down by short to GND. C
Table 4-6 Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
VCC 1 DRV5056-Q1 will not be damaged. There will be no power supply current and therefore no functionality. B
GND 2 DRV5056-Q1 will not be damaged. There will be no power supply current and therefore no functionality. B
OUT 3 DRV5056-Q1 will not be damaged. Supply current will be normal, but the output is not driving any load. C
Table 4-7 Pin FMA for Device Pins Short-Circuited to supply
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
VCC 1 Normal mode of operation D
GND 2 Supply shorted to Ground. System will source high current as a result and may current limit. Thermal damage may result. B
OUT 3 DRV5056-Q1 will not be damaged. The output will sink about 14 mA (limited by overcurrent protection feature). The output signal will be pulled to VCC. Any MCU monitoring the output would observe VCC as an input which may result in over voltage. B