SFFS757 February   2024 DLP4620S-Q1 , DLPC231S-Q1

 

  1.   1
  2. 1Introduction
    1.     Trademarks
  3. 2 DLP4620S-Q1 Chipset Functional Safety Capability
  4. 3Development Process for Management of Systematic Faults
    1. 3.1 TI New-Product Development Process
    2. 3.2 TI Functional Safety Development Process
  5. 4 DLP4620S-Q1 Chipset Overview
    1. 4.1 Targeted Applications
    2. 4.2 DLP4620S-Q1 Chipset Functional Safety Concept
      1. 4.2.1 Typical Hazards
      2. 4.2.2 Chipset Architecture
      3. 4.2.3 Built-In Self Tests
    3. 4.3 Functional Safety Constraints and Assumptions
  6. 5Description of Hardware Component Parts
    1. 5.1 Description of System Level Built In Self Test (BISTs)
  7. 6Management of Random Faults
    1. 6.1 Fault Reporting
      1. 6.1.1 HOST_IRQ
      2. 6.1.2 Error History
      3. 6.1.3 Fault Handling
    2. 6.2 Functional Safety Mechanism Categories
    3. 6.3 Description of Functional Safety Mechanisms
      1. 6.3.1 Video Path Protection
        1. 6.3.1.1 Video Input BISTs
        2. 6.3.1.2 Video Processing BISTs
        3. 6.3.1.3 Video Output BISTs
      2. 6.3.2 Illumination Control Protection
        1. 6.3.2.1 Communication Interface and Register Protection
        2. 6.3.2.2 LED Control Feedback Loop Protection
        3. 6.3.2.3 Data Load and Transfer Protection
        4. 6.3.2.4 Watchdogs and Clock Monitors
        5. 6.3.2.5 Voltage Monitors
  8.   A Summary of Recommended Functional Safety Mechanism Usage
  9.   B Distributed Developments
    1.     B.1 How the Functional Safety Lifecycle Applies to TI Functional Safety Products
    2.     B.2 Activities Performed by Texas Instruments
    3.     B.3 Information Provided
  10.   C Revision History

5 Description of Hardware Component Parts

A semiconductor component can be divided into parts to enable a more granular functional safety analysis. This can be useful to help assign specific functional safety mechanisms to portions of the design where they provide coverage ending up with a more complete and customizable functional safety analysis. This section includes a brief description of the various blocks of the three chipset components. The quantitative functional safety analysis is done according to these partitions. Partitions for each device are given in the tables below.

Table 5-1 DLPC231S-Q1 Blocks
Block Name Block Function
VGP Video and Graphics Processor. Receives input video data and generates splash images or test patterns. Performs video processing functions such as scaling and color space conversion.
RTP Real-Time Processor. ARM micro-processor core and related memories.
RSC Real-Time System Control. Timing control for LEDs, DMD mirror transitions, and ADC measurements. Includes hardware processing blocks and associated memories.
FMT Formatter and Universal Memory Controller. Converts data output from the VGP into single color images that are displayed on the DMD. Includes the SRAM frame buffers. Data is received from the VGP, processed, and stored into the frame buffer. Data is output from the frame buffer to the DMD based on instructions from the RSC.
SSF Clock generation for various clock domains in the DLPC231S-Q1.
DDI DMD data interface. High speed interface for outputting data from DLPC231S-Q1 to DMD.
FPD OpenLDI input video port.
RTP BROM Boot ROM that initiates loading of software from external flash to internal RAM and performs boot tests.
Table 5-2 TPS99000S-Q1 Blocks
Block Name Block Function
AAC ADC control including the TPS99000S-Q1 to DLPC231S-Q1 AD3 interface.
CSR Configuration status registers.
DEG Deglitching for signals.
DTV Data transfer validation. DLPC231S-Q1 to TPS99000S-Q1 SPI port and related functions.
ILM Illumination control.
PSC Power state controller.
SSF Secondary SPI port for diagnostics.
ROM ROM used for storing device trim data.
Table 5-3 DLP4620S-Q1 Blocks
Block Name Block Function
SRAM SRAM cells under micro-mirror layer. Data loaded into SRAM determines state of each mirror.
IO High speed interface that receives the video data from the DLPC231S-Q1.
SCTRL Instruction decoder for data received over IO.
Reset Ctrl Mirror transition control.
LSIF Low speed interface for DMD configuration and mirror reset voltage control.