SFFS779 December 2024 TMS320F28P550SJ
The dual-clock comparator module can be used to validate or monitor the output frequency of the PLL (PLLRAWCLK) over a defined time window. While checking for the PLL clock frequency, DCC uses a known good reference clock to compare with, which is INTOSC1, INTOSC2, or XTAL. If the PLL clock frequency deviates from the targeted frequency more than a predefined threshold, DCC reports an ERROR status flag and sends an interrupt to the PIE.
Proper operation of dual clock comparator (DCC) functionality can be checked by configuring DCC with a wrong ratio between counter 0 (DCCCNTSEED0) and counter 1 (DCCCNTSEED1) to force a failure. The fail flag interrupt can then be checked to verify the functionality of DCC.