Once enabled,
prefetch logic keeps fetching the next 128-bit row (4 x
32-bit words) from flash bank. On detecting the
discontinuity, the prefetch buffer is cleared. A software
test can be performed to ascertain the proper behavior of
this logic. The following operation sequence can be
performed:
- Disable
the prefetch mechanism, enable the timer and
watchdog. Execute a particular function which has
linear code and code with multiple
discontinuities. Store the time taken for
executing this function, as time_1 (timer
value).
- Enable
the prefetch mechanism and execute the same
function again. Store the time taken for executing
this function, as time_2 (timer value). This value
must be less than the time_1 (time_1 > time_2).
We can mark this timer value as a golden
value and expect the same timer values for each
run of the same function.
- Since
each flash bank row has 4 x 32-bit words, number
of rows fetched from the flash bank varies, as per
the code alignment within the flash bank. Hence,
users must verify that the prefetch logic test
function is aligned and located in a particular
location within flash to maintain the same timing
behavior and does not vary compile to compile.
Similar timer-based
profiling can be performed to ascertain proper functioning
of the data cache and wait states.