SFFS779 Functional safety information

SFFS779 December 2024 TMS320F28P550SJ

5.1.2 Clock

The C2000 MCU device family products are primarily synchronous logic devices and as such require clock signals for proper operation. The clock management logic includes clock sources, clock generation logic including clock multiplication by phase lock loops (PLLs), clock dividers, and clock distribution logic. The registers that are used to program the clock management logic are located in the system control module. The following tests can be applied as diagnostics for this module (to provide diagnostic coverage on a specific function):

Note:

DCC is the recommended method of clock monitoring over the CPU timer or HRPWM-based methods.
TI recommends the use of an external watchdog over an internal watchdog for mitigating the risk due to common mode failure. TI also recommends the use of a program sequence, windowed, or question and answer watchdog as opposed to a single-threshold watchdog due to the additional failure modes that can be detected by a more advanced watchdog.
Driving a high-frequency clock output on the XCLKOUT pin can have EMI implications. The selected clock must be scaled appropriately before sending out through I/O.