SFFS799 March 2024 TLV365-Q1

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the TLVx365-Q1 (SOT-23 and SOIC packages). The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to ground (see Table 4-2 and Table 4-6)
Pin open-circuited (see Table 4-3 and Table 4-7)
Pin short-circuited to an adjacent pin (see Table 4-4 and Table 4-8)
Pin short-circuited to V+ (see Table 4-5 and Table 4-9)

Table 4-2 through Table 4-9 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality
B	No device damage, but loss of functionality
C	No device damage, but performance degradation
D	No device damage, no impact to functionality or performance

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

Total supply voltage of 5V with V+ connected to 5V and V- connected to ground.
Input and output pins biased to 2.5V reference point.
Device is configured with feedback network in gain greater than or equal to 1V/V.