SFFS819 May   2024 RES11A-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1  SOT-23-THIN Package: RES11A10-Q1
    2. 2.2  SOT-23-THIN Package: RES11A15-Q1
    3. 2.3  SOT-23-THIN Package: RES11A16-Q1
    4. 2.4  SOT-23-THIN Package: RES11A20-Q1
    5. 2.5  SOT-23-THIN Package: RES11A25-Q1
    6. 2.6  SOT-23-THIN Package: RES11A30-Q1
    7. 2.7  SOT-23-THIN Package: RES11A40-Q1
    8. 2.8  SOT-23-THIN Package: RES11A50-Q1
    9. 2.9  SOT-23-THIN Package: RES11A90-Q1
    10. 2.10 SOT-23-THIN Package: RES11A00-Q1
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the RES11A-Q1 (SOT-23-THIN). The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
Class Failure Effects
A Potential device damage that affects functionality
B No device damage, but loss of functionality
C No device damage, but performance degradation
D No device damage, no impact to functionality or performance

Figure 4-1 shows the RES11A-Q1 pin diagram for the SOT-23-THIN package. For a detailed description of the device pins, see the Pin Configuration and Functions section in the RES11A-Q1 data sheet.

Figure 4-1 Pin Diagram for SOT-23-THIN Package

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • 'Short circuit to VEE or Ground' means short to GND/SUB

  • 'Short circuit to Supply or VCC' means shorted to a source of power at a different potential than GND/SUB

  • 'Divider 1' means the circuit of RIN1, RMID1, and RG1

  • 'Divider 2' means the circuit of RIN2, RMID2, and RG2

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground (VEE)
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
RIN1 1 RIN1 is set to VEE. Device functions as intended if VEE‒VRG1 does not exceed maximum rating. A
RMID1 2 RMID1 is set to VEE. Device functions as intended if VEE‒VRIN1 and VEE‒VRG1 do not exceed maximum ratings. A
RG1 3 RG1 is set to VEE. Device functions as intended if VEE‒VRIN1 does not exceed maximum rating. A
GND 4 If GND2 is left floating, the device substrate is biased to VEE and functions as intended. If GND2 is also biased, then voltage can develop across the substrate, potentially damaging the device. If both GND1 and GND2 are short circuited, a current path can form through the substrate, potentially damaging the device. A
GND 5 If GND1 is left floating, the device substrate is biased to VEE and functions as intended. If GND1 is also biased then voltage can develop across the substrate, potentially damaging the device. If both GND1 and GND2 are short circuited, a current path can form through the substrate, potentially damaging the device. A
RIN2 6 RIN2 is set to VEE. Device functions as intended if VEE‒VRG2 does not exceed maximum rating. A
RMID2 7 RMID2 is set to VEE. Device functions as intended if VEE‒VRIN2 and VEE‒VRG2 do not exceed maximum rating. A
RG2 8 RG2 is set to VEE. Device functions as intended if VEE‒VRIN2 does not exceed maximum rating. A
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
RIN1 1 No impact on performance, resistor is left floating. Device remains functional. Divider 1 midpoint voltage is unreliable B
RMID1 2 No impact on device functionality. Divider 2 midpoint is unable to be read by external circuitry D
RG1 3 No impact on performance, resistor is left floating. Device remains functional. Divider 1 midpoint voltage is unreliable B
GND1 4 Depending on circuit configuration, circuit noise is increased and device bandwidth is increased. C
GND2 5 Depending on circuit configuration, circuit noise is increased and device bandwidth is increased. C
RIN2 6 No impact on performance, resistor is left floating. Device remains functional. Divider 2 midpoint voltage is unreliable B
RMID2 7 No impact on device functionality. Divider 2 midpoint is unable to be read by external circuitry D
RG2 8 No impact on performance, resistor is left floating. Device remains functional. Divider 2 midpoint voltage is unreliable B
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Description of Potential Failure Effects Failure Effect Class
RIN1 1 RMID1 RIN1 resistance is forced into short circuit condition with VMID1 voltage ultimately forced to VRIN1 voltage. The voltage between VRIN1 and VRG1 must not exceed maximum voltage rating or device damage will occur. B
RMID1 2 RG1 RG1 resistance is forced into short circuit condition with VMID1 voltage ultimately forced to VRG1 voltage. The voltage between VRIN1 and VRG1 must not exceed maximum voltage rating or device damage will occur. B
RG1 3 GND1 If GND2 is floating then the substrate is biased to VRG1 and functions as intended. If GND2 is also biased then voltage can develop across the substrate potentially damaging the device. A
GND1 4 GND2 GND1 and GND2 are short circuited and a current return path forms through the substrate potentially damaging the device. A
GND2 5 RIN2 If GND1 is floating then the substrate is biased to VRIN2 and functions as intended. If GND1 is also biased then voltage can develop across the substrate potentially damaging the device. A
RIN2 6 RMID2 RIN2 resistance is forced into short circuit condition with VMID2 voltage ultimately forced to VRIN2 voltage. The voltage between VRIN2 and VRG2 must not exceed maximum voltage rating or device damage will occur. B
RMID2 7 RG2 RG2 resistance is forced into short circuit condition with VMID2 voltage ultimately forced to VRG2 voltage. The voltage between VRIN2 and VRG2 must not exceed maximum voltage rating or device damage will occur. B
RG2 8 RIN1 Device inputs are shorted together leaving the RG2 pin and RIN1 pin at some voltage between VRG1 and VRIN2. The device functions as intended if VRG2‒VMID2 and VRIN1‒VMID1 do not exceed maximum rating. B
Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply (VCC)
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
RIN1 1 RIN1 is set to VCC. Device functions as intended if VCC‒VRG1 does not exceed maximum rating. A
RMID1 2 RMID1 is set to VCC. Device functions as intended if VCC‒VRIN1 and VCC‒VRG1 do not exceed maximum rating. A
RG1 3 RG1 is set to VCC. Device functions as intended if VCC‒VRIN1 does not exceed maximum rating. A
GND1 4 If GND2 is left floating, the device substrate is biased to VCC and functions as intended. If GND2 is also biased then voltage can develop across the substrate, potentially damaging the device. If both GND1 and GND2 are short circuited, a current path can form through the substrate, potentially damaging the device. A
GND2 5 If GND1 is left floating, the device substrate is biased to VCC and functions as intended. If GND1 is also biased then voltage can develop across the substrate, potentially damaging the device. If both GND1 and GND2 are short circuited, a current path can form through the substrate, potentially damaging the device. A
RIN2 6 RIN2 is set to VCC. Device functions as intended if VCC‒VRG2 does not exceed maximum rating. A
RMID2 7 RMID2 is set to VCC. Device functions as intended if VCC‒VRIN2 and VCC‒VRG2 do not exceed maximum rating. A
RG2 8 RG2 is set to VCC. Device functions as intended if VCC‒VRIN2 does not exceed maximum rating. A