SFFS832 September 2024 UCC27301A-Q1 , UCC27311A-Q1
4.2 VSON Package
Figure 4-2 shows the UCC273x1A-Q1 pin diagram for the VSON package. For a detailed description of the device pins, see the Pin Configuration and Functions section in the UCC273x1A-Q1 data sheet.
Figure 4-2 Pin Diagram (VSON Package)Table 4-6 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| VDD | 1 | No power is applied to the device. HO and LO are in a low state. | B |
| NC | 2 | No impact. | D |
| HB | 3 | HO and LO are in unknown state. | A |
| HO | 4 | HO and LO are in unknown state. | A |
| HS | 5 | HO and LO are in unknown state. | A |
| EN | 6 | HO and LO are in a low state. | B |
| HI | 7 | HO is in a low state. | B |
| LI | 8 | LO is in a low state. | B |
| VSS | 9 | N/A | D |
| LO | 10 | HO and LO are in unknown state. | A |
Table 4-7 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| VDD | 1 | No power is applied to the device. HO and LO are in a low state. | B |
| NC | 2 | No impact. | D |
| HB | 3 | HO is pulled to HS potential. | B |
| HO | 4 | HO is disconnected from the system. | B |
| HS | 5 | HO is pulled to HB potential. | B |
| EN | 6 | HO and LO are in a low state. | B |
| HI | 7 | HO is in a low state. | B |
| LI | 8 | LO is in a low state. | B |
| VSS | 9 | HO is in a low state. LO is pulled to VDD. | B |
| LO | 10 | LO is disconnected from the system. | B |
Table 4-8 Pin FMA for Device Pins
Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| VDD | 1 | NC | No impact | D |
| NC | 2 | HB | No impact | D |
| HB | 3 | HO | HO is in unknown state. | A |
| HO | 4 | HS | HO is in unknown state. | A |
| HS | 5 | N/A | N/A | D |
| EN | 6 | HI | HO and LO follows the logic truth table per the data sheet with EN and HI same potential. The logic states of EN and HI depends on the system. | B |
| HI | 7 | LI | HO and LO follows the logic truth table per the data sheet with LI and HI same potential. The logic states of EN and HI depends on the system. | B |
| LI | 8 | VSS | LO is in a low state. | B |
| VSS | 9 | LO | LO is in unknown state. | A |
| LO | 10 | N/A | N/A | D |
Table 4-9 Pin FMA for Device Pins Short-Circuited to
Supply
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| VDD | 1 | N/A | D |
| NC | 2 | N/A | D |
| HB | 3 | HO and LO are in unknown state. | A |
| HO | 4 | HO and LO are in unknown state. | A |
| HS | 5 | HO and LO are in unknown state. | A |
| EN | 6 | LO and HO follow the truth table specified in the data sheet with EN stuck in a high state. | B |
| HI | 7 | LO and HO follow the truth table specified in the data sheet with HI stuck in a high state. | B |
| LI | 8 | LO and HO follow the truth table specified in the data sheet with LI stuck in a high state. | B |
| VSS | 9 | Supply short condition. LO and HO states depend on the system. If VSS is pulled to VDD, LO is pulled to VDD and HO is in a low state. | B |
| LO | 10 | HO and LO are in unknown state. | A |