SFFS858 December 2024 LMR60410
This section provides a failure mode analysis (FMA) for the pins of the LMR60406, LMR60406-Q1, LMR60410, and LMR60410-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Class | Failure Effects |
---|---|
A | Potential device damage that affects functionality. |
B | No device damage, but loss of functionality. |
C | No device damage, but performance degradation. |
D | No device damage, no impact to functionality or performance. |
Figure 4-1 shows the LMR60406, LMR60406-Q1, LMR60410, and LMR60410-Q1 pin diagram. For a detailed description of the device pins, see the Pin Configuration and Functions section in the LMR60406, LMR60406-Q1, LMR60410, and LMR60410-Q1 data sheet.
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
---|---|---|---|
VIN | 1 | VOUT = 0V. | B |
PGND | 2 | VOUT is normal. | D |
SW | 3 | Damage to high-side FET. | A |
BOOT | 4 | VOUT = 0V. High-side FET does not turn on. | B |
PG | 5 | When not in use, this pin can be left grounded (PG is not a valid signal and VOUT is normal). | D |
FB | 6 | When in adjustable output mode, VOUT approaches VIN. When in fixed output mode, VOUT = 0V. | B |
MODE/SYNC | 7 | Device switches in AUTO mode. VOUT is normal. | D |
RT | 8 | Device stops switching until short to GND is removed. | B |
EN | 9 | VOUT = 0V. Enable is below the VEN-TH and functionality is halted. | D |
Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
---|---|---|---|
VIN | 1 | VOUT = 0V. | B |
PGND | 2 | VOUT can be abnormal. | C |
SW | 3 | VOUT = 0V. | B |
BOOT | 4 | VOUT = 0V. High-side FET does not turn on. | B |
PG | 5 | When not in use, this pin can be left open (PGOOD is not a valid signal and VOUT is normal). | D |
FB | 6 | VOUT approaches VIN. | C |
MODE/SYNC | 7 | Mode of operation can toggle between AUTO and FPWM. | C |
RT | 8 | Internal clock does not operate properly and the part does not switch. | B |
EN | 9 | Pin cannot be left floating. Device potentially does not enable. | B |
Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
---|---|---|---|---|
VIN | 1 | PGND | VOUT = 0V. | B |
PGND | 2 | SW | Damage to high-side FET. | A |
SW | 3 | BOOT | VOUT = 0V, high-side FET does not turn on and there is not CBOOT. | B |
BOOT | 4 | PG | PG damage occurs if BOOT voltage is greater than PG absolute maximum voltage. | B |
PG | 5 | FB | In fixed output mode, VOUT = 0V. In adjustable mode, if a short happens before soft state is complete, output voltage approaches input voltage supply. | B |
FB | 6 | PGND | In fixed output mode, VOUT = 0V. In adjustable output mode, output voltage approaches the input voltage supply. | B |
MODE/SYNC | 7 | RT | Device operates in FPWM. | D |
RT | 8 | EN | Internal clock does not switch at the correct frequency. | C |
EN | 9 | VIN | Device is enabled once the voltage between VIN and PGND is greater than VINUVLO(R). | D |
Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
---|---|---|---|
VIN | 1 | VOUT is normal. | D |
PGND | 2 | VOUT = 0V. | B |
SW | 3 | Damage to low-side FET. | A |
BOOT | 4 | Damage occurs to BOOT ESD. | A |
PG | 5 | If supply voltage is greater than 20V, damage occurs to PGOOD pin. | A |
FB | 6 | If supply voltage is greater than 16V, damage occurs. | A |
MODE/SYNC | 7 | Device operates in FPWM. | D |
RT | 8 | Internal clock does not switch at the correct frequency. | C |
EN | 9 | VOUT is normal. | D |