Once enabled, prefetch logic keeps fetching the
next 128-bit row (4 x 32-bit words) from flash bank. On detecting a
discontinuity, the prefetch buffer is cleared. A software test can
be performed to ascertain the proper behavior of this logic. The
following sequence of operations can be performed.
- Disable the prefetch mechanism, enable the timer
and watchdog. Execute a particular function which might have
linear code and code with multiple discontinuities. Store
the time “time_1” (timer value) taken for executing this
function.
- Enable the prefetch mechanism and execute the
same function again. Store the time “time_2” (timer value)
taken for executing this function. This value must be less
than time_1 (time_1 > time_2). We can mark this timer
value as a golden value and should expect the same timer
values for each run of the same function.
- Since each flash bank row has 4 x 32-bit words,
the number of rows fetched from the flash bank varies with
the code alignment within the flash bank. Hence, users need
to verify that the prefetch logic test function is properly
aligned and located in a particular location within flash to
generate timing behavior that does not vary from compile to
compile.
Similar timer-based profiling can be performed to
ascertain proper functioning of the data cache and Wait states.