SFFS993 October   2024 LMR51403

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)

Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the LMR51403. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality.
BNo device damage, but loss of functionality.
CNo device damage, but performance degradation.
DNo device damage, no impact to functionality or performance.

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • Device used within the Recommended Operating Conditions and the Absolute Maximum Ratings found in the appropriate device data sheet.
  • Configuration as shown in the Example Application Circuit found in the appropriate device data sheet.

Figure 4-1 shows the LMR51403 pin diagram for the SOT-23 package. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the appropriate device data sheet.

LMR51403 Pin
                    Diagram Figure 4-1 Pin Diagram
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
CB1No output voltage.B
GND2Normal operation.D
FB3The regulator operates at maximum duty cycle. Output voltage rises approximately to the input voltage (VIN) level. Damage to customer load and output stage components are possible. No effect on device.B
EN4Loss of ENABLE functionality. Device remains in shutdown mode.B
VIN5Device does not operate. No output voltage is generated. Output capacitors discharge through the input short. A large current reversal can damage the device.A
SW6Damage to internal FET.A
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
CB1No output voltage.B
GND2VOUT can be abnormal due to switching noise on analog circuits.B
FB3VOUT is higher than the programmed output voltage.B
EN4Loss of ENABLE functionality. Erratic operation; loss of regulation is probable.B
VIN5No output voltage.B
SW6No output voltage.B
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure EffectsFailure Effect Class
CB1GNDNo output voltage.A
GND2FBThe regulator operates at maximum duty cycle. Output voltage rises approximately to the input voltage (VIN) level. Damage to customer load and output stage components are possible. No effect on device.B
FB3GNDThe regulator operates at maximum duty cycle. Output voltage rises approximately to the input voltage (VIN) level. Damage to customer load and output stage components are possible. No effect on device.B
EN4VINNo damage to device. Loss of ENABLE functionality.B
VIN5SWDamage to internal FET.A
SW6VINDamage to internal FET.A
Table 4-5 Pin FMA for Device Pins Short-Circuited to VIN
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
CB1No output voltage. CBOOT ESD clamp runs current to destruction.A
GND2No output voltage. Damage to other pins referred to GND.A
FB3If VIN exceeds 5.5V, damage occurs. No output voltage.A
EN4No damage to device. Loss of ENABLE functionality.B
VIN5No effect.D
SW6Damage to low side MOSFET.A